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I'm a PhD student fighting in network and system area, but have a heart of geek.
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Tsinghua University
- guanyu.li
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FiveStage-MIPS-CPU
FiveStage-MIPS-CPU PublicComplete a 5-stage MIPS CPU with multi-level interrupts and dynamic branch prediction on logisim and verilog
Verilog 2
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SingleCycle-MIPS-CPU
SingleCycle-MIPS-CPU PublicComplete a single-cycle MIPS CPU on logisim
Assembly
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