This repository contains reports from university projects involving ForwardCom.
Kai Rese: Experimental characterization of the effect of various ForwardCom architecture parameters on microprocessor performance. Hochschule Niederrhein, Germany, 2023.
Abstract: This thesis provides a first examination of some experimental design parameters of the ForwardCom instruction set architecture. It tests the performance impact of these parameters via an experiment. The experiment was performed using two benchmark programs, simulated on two CPU models via the General Purpose Core Architecture Simulator. The parameter impact is derived by allowing or disallowing the corresponding feature, then testing each feature combination and extracting the performance difference of allowing each feature for each combination of the others. The used benchmarks programs are N-body and Mandelbrot. The tested parameters are multi-word formats, ALU-and-branch instructions, instructions with a memory operand, variable vector length support, and vector loops. Due to the small sample size of benchmark programs and CPU models, the experiment results contain some large variations. Because neither a compiler nor a complete hardware implementation of ForwardCom exist yet, the thesis cannot provide a predictive result, but it can provide a first rough indication as a pilot study. Taking this limitation into account, the results show a significant positive performance impact of each tested feature, as well as for feature combinations. The results of all features combined range from a 26% improvement up to a 80% improvement, ignoring the increased flexibility for size in vector unit implementations. Taking that into account, improvements of up to 623% are observed.
An architecture simulator developed by Kai Rese is maintained at a separate git site