Skip to content

Issues: Juniper/open-register-design-tool

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

23 Open 62 Closed
23 Open 62 Closed
Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

How to dump JSON file from a rdl?
#91 opened Nov 19, 2021 by EngRaff92
Build in Debian/testing does not work
#89 opened Aug 18, 2021 by wzab
1
Struct Generation not working
#88 opened Feb 25, 2021 by abagchi
Sticky interrupt with hardware precedence and write-one-to-clear can not be cleared
#87 opened Dec 15, 2020 by tenaliram
addressing and alignment properties of addressmap not being followed
#85 opened Aug 25, 2020 by tenaliram
1
Control bit-width of address bus in addrmap
#84 opened Aug 16, 2020 by tenaliram
2
Cannot get Ordt-viewer to work
#83 opened Jun 25, 2020 by jyaghutiel
clock gating issue
#82 opened May 7, 2020 by xinhui-zhang
When there is a secondary processor, decoder logic is out of sync.
#81 opened Apr 14, 2020 by kongty
Is there an option to enable address channel for each write and read, instead of one address channel?
#80 opened Apr 10, 2020 by kongty
How to have holding registers
#79 opened Feb 25, 2020 by tkafafi
External Reset signals Causing RTL generation to fail
#78 opened Dec 19, 2019 by neenuprince
2
Is there an option to enable or disable the flopping of inputs and/or outputs to the RTL generated?
#75 opened Oct 18, 2019 by neenuprince
1
How to connect the APB bus to the generated verilog module？
#73 opened Aug 21, 2019 by zhajio1988
3
New commits will be made to the sdnellen fork
#71 opened Jul 30, 2019 by sdnellen
RTl code has floating signals for HWRead SWwrite registers causing X's
#70 opened Jul 18, 2019 by neenuprince
2
Register field ordering is broken.
#69 opened Jul 2, 2019 by sjalloq
2
Ordt should generate an error on { sw=rw; hw=w; } with no hw we.
#68 opened Jun 14, 2019 by sjalloq
1
Build error from source
#63 opened Jun 11, 2019 by sjalloq
2
Incomplete reset specification on external register interface
#62 opened Jun 6, 2019 by petenixon
5
XML Data Dictionary
#52 opened Dec 5, 2018 by WebMonkey007
2
Add support for callbacks to cppmod output
#36 opened Nov 9, 2017 by ebertland
3
Feature Request: C header file output
#22 opened Sep 5, 2017 by ebertland
3
ProTip! no:milestone will show everything without a milestone.