Hm2 bspi fixes #2288

…buffer present

The BSPI module has a receive fifo and a transmit fifo per instance (shared among all the channels of that instance). Writing anything to the fifo count register clears both fifos, discarding any old read data and any pending write data.

Writing to BSPI channels with echo enabled also simultaneously reads from those channels. The read bytes go into the BSPI instance's read fifo, where they stay until the driver reads them out. By writing to the (echo-y) ADCs to configure them, we also put some bytes into the read fifo. When we later try to read the analog and digital inputs, we'll actually get the old bytes from the ADC setup, and everything will be off by a handful of bytes, resulting in incorrect information being used. This commit fixes the problem by clearing the FIFO after setting up the ADCs. There may be another bug lurking in here - if somehow the FIFO becomes out of sync, we'll never recover. A future hacker will get the pleasure of rediscovering this problem and fixing it.

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Hm2 bspi fixes #2288

Hm2 bspi fixes #2288

Commits on Jan 18, 2023