Avalon

This repo contains various utilities for Avalon Memory Map. This is an industry standard bus interface for connecting peripherals (e.g. memory and I/O devices) to a bus master (e.g. a CPU).

Avalon Memory Map interface

Here is a brief summary of the signals involved in the Avalon Memory Map interface. For full details, refer to Section 3 of the specification. These blocks all use "Pipelined Read Transfer with Variable Latency", see section 3.5.4 and Figure 12, and support burst mode, see section 3.5.5. They do not use the "waitrequestAllowance" property.

Signal	Description
`write`	Asserted by client when sending data to the device.
`read`	Asserted by client when requesting data from the device.
`address`	The address (in units of words).
`writedata`	The data to send to the device.
`byteenable`	1-bit for each byte of data to the device.
`burstcount`	Number of words to transfer.
`readdata`	Data receive from the device.
`readdatavalid`	Asserted when data from the device is valid.
`waitrequest`	Asserted by the device when it is busy.

`avm_memory.vhd`

This generates a block of memory (BRAM).

`avm_master.vhd`

This acts as an Avalon Master (instead of a CPU) to generate some test trafic.

`avm_decrease.vhd`

This utility connects a Master and a Slave, where the two have different data widths. Specifically, the Master data width is expected to be larger than the Slave data width. A single Master request is converted into a burst mode request to the Slave.

`avm_pause.vhd`

This inserts small pauses into the Avalon Memory Map interface. This is useful to increase test coverage.

Name		Name	Last commit message	Last commit date
Latest commit History 94 Commits
Avalon_Interface_Specifications.pdf		Avalon_Interface_Specifications.pdf
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
avalon_axi.vhd		avalon_axi.vhd
avm_arbit.gtkw		avm_arbit.gtkw
avm_arbit.psl		avm_arbit.psl
avm_arbit.sby		avm_arbit.sby
avm_arbit.vhd		avm_arbit.vhd
avm_cache.gtkw		avm_cache.gtkw
avm_cache.psl		avm_cache.psl
avm_cache.sby		avm_cache.sby
avm_cache.vhd		avm_cache.vhd
avm_decrease.vhd		avm_decrease.vhd
avm_fifo.vhd		avm_fifo.vhd
avm_increase.gtkw		avm_increase.gtkw
avm_increase.psl		avm_increase.psl
avm_increase.sby		avm_increase.sby
avm_increase.vhd		avm_increase.vhd
avm_master.vhd		avm_master.vhd
avm_master2.gtkw		avm_master2.gtkw
avm_master2.psl		avm_master2.psl
avm_master2.sby		avm_master2.sby
avm_master2.vhd		avm_master2.vhd
avm_master3.vhd		avm_master3.vhd
avm_master_general.vhd		avm_master_general.vhd
avm_memory.vhd		avm_memory.vhd
avm_memory_pause.vhd		avm_memory_pause.vhd
avm_pause.gtkw		avm_pause.gtkw
avm_pause.psl		avm_pause.psl
avm_pause.sby		avm_pause.sby
avm_pause.vhd		avm_pause.vhd
avm_pipe.psl		avm_pipe.psl
avm_pipe.sby		avm_pipe.sby
avm_pipe.vhd		avm_pipe.vhd
axi_avalon.vhd		axi_avalon.vhd
axi_expander.gtkw		axi_expander.gtkw
axi_expander.psl		axi_expander.psl
axi_expander.sby		axi_expander.sby
axi_expander.vhd		axi_expander.vhd
axi_fifo.vhd		axi_fifo.vhd
axi_fifo_small.vhd		axi_fifo_small.vhd
axi_gcr.vhd		axi_gcr.vhd
axi_merger.gtkw		axi_merger.gtkw
axi_merger.psl		axi_merger.psl
axi_merger.sby		axi_merger.sby
axi_merger.sh		axi_merger.sh
axi_merger.vhd		axi_merger.vhd
axi_shrinker.gtkw		axi_shrinker.gtkw
axi_shrinker.psl		axi_shrinker.psl
axi_shrinker.sby		axi_shrinker.sby
axi_shrinker.vhd		axi_shrinker.vhd
axi_skid_buffer.vhd		axi_skid_buffer.vhd
burst_ctrl.vhd		burst_ctrl.vhd
lfsr.vhd		lfsr.vhd
random.vhd		random.vhd
tb_avalon_axi.gtkw		tb_avalon_axi.gtkw
tb_avalon_axi.vhd		tb_avalon_axi.vhd
tb_avm_arbit.gtkw		tb_avm_arbit.gtkw
tb_avm_arbit.vhd		tb_avm_arbit.vhd
tb_avm_arbit2.vhd		tb_avm_arbit2.vhd
tb_avm_cache.gtkw		tb_avm_cache.gtkw
tb_avm_cache.vhd		tb_avm_cache.vhd
tb_avm_cache2.gtkw		tb_avm_cache2.gtkw
tb_avm_cache2.vhd		tb_avm_cache2.vhd
tb_avm_decrease.gtkw		tb_avm_decrease.gtkw
tb_avm_decrease.vhd		tb_avm_decrease.vhd
tb_avm_increase.gtkw		tb_avm_increase.gtkw
tb_avm_increase.vhd		tb_avm_increase.vhd
tb_avm_master2.gtkw		tb_avm_master2.gtkw
tb_avm_master2.vhd		tb_avm_master2.vhd
tb_avm_master3.gtkw		tb_avm_master3.gtkw
tb_avm_master3.vhd		tb_avm_master3.vhd
tb_avm_pipe.gtkw		tb_avm_pipe.gtkw
tb_avm_pipe.vhd		tb_avm_pipe.vhd
tb_axi_gcr.gtkw		tb_axi_gcr.gtkw
tb_axi_gcr.vhd		tb_axi_gcr.vhd
tb_axi_shrinker_expander.gtkw		tb_axi_shrinker_expander.gtkw
tb_axi_shrinker_expander.vhd		tb_axi_shrinker_expander.vhd
tb_burst_ctrl.gtkw		tb_burst_ctrl.gtkw
tb_burst_ctrl.vhd		tb_burst_ctrl.vhd

License

MJoergen/Avalon

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