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how to update config.json when my design with two clock input with different frequence?

TonyHo722 asked Oct 24, 2023 in Q&A · Answered

2
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Using a slice of a multi-bit port as clock name

scorbetta asked Mar 19, 2024 in Q&A · Answered

1
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Constraining a synchronizer

scorbetta asked Mar 29, 2024 in Q&A · Unanswered

0
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Error pdn-0175 (pitch is too small)

krissjarvis asked May 2, 2023 in Q&A · Unanswered

5
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Installation problem: can't find flow.tcl after run "make test"

doctor-TZ asked Jan 28, 2024 in Q&A · Unanswered

1
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Magic DRC Errors

tdtu1002 asked Nov 18, 2023 in Q&A · Unanswered

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ORFS Check antenna: Command terminated by signal 6

marcopoles asked Oct 19, 2023 in Q&A · Unanswered

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ERROR: Re-definition of module `\para_ser_01'!

yslim2002 asked Sep 18, 2023 in Q&A · Unanswered

3
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OpenLane quit at synthesis stage but no apparent error

heliboy2003 asked Aug 7, 2023 in Q&A · Closed · Unanswered

1
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SPEF extraction in interactive mode

akhilesh911 asked Aug 1, 2023 in Q&A · Unanswered

4
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Slew margin in openlane flow

akhilesh911 asked Jul 28, 2023 in Q&A · Closed · Answered

11
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Dockerized Openlane - yosis systemverilog support

Andrea-Spitale asked Jul 16, 2023 in Q&A · Unanswered

1
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Error IR Drop in caravel_user_project with an OpenFPGA

CristopherA96 asked Jun 19, 2023 in Q&A · Unanswered

3
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Error with verilator lint check process in latest Openlane's version

CristopherA96 asked May 3, 2023 in Q&A · Unanswered

2
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Errors working witn OpenFPGA files in latest Version of OpenLane

CristopherA96 asked May 3, 2023 in Q&A · Unanswered

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Where is pdk folder?

eusanchez asked Apr 20, 2023 in Q&A · Closed · Unanswered

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sta.tcl script, trying to show all scripts in max and min reports

eusanchez asked Apr 4, 2023 in Q&A · Unanswered

2
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OpenLane vs OpenROAD

Sinbiosis asked Feb 3, 2022 in Q&A · Closed · Answered

13
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What does yosys -import do?

xobs asked Apr 10, 2023 in Q&A · Answered

3
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Error when 'make' command is given

Shrihari01 asked Feb 27, 2023 in Q&A · Closed · Answered

1
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Effect of SYNTH_NO_FLAT

hmzsaeed asked Dec 26, 2022 in Q&A · Answered

7
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Which RCX extractor rules to use?

vijayank88 asked Nov 9, 2022 in Q&A · Answered

4
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SYNTH_STRATEGY usage

vijayank88 asked Feb 25, 2022 in Q&A · Answered

2
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how to work with multiple verilog files

IngYordiDelgado asked Sep 10, 2022 in Q&A · Unanswered

3
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What is the recommended way to handle OpenRAM macro DRCs in OpenLane.

armleo asked Aug 29, 2022 in Q&A · Unanswered

0