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@airhdl

airhdl

Web-based VHDL/SystemVerilog AXI4 register generator for FPGA and ASIC projects.
README.md

A web-based VHDL/SystemVerilog AXI4 register bank generator for FPGA and ASIC projects. Sign-up for free at airhdl.com.

Pinned

  1. spi-to-axi-bridge spi-to-axi-bridge Public

    An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

    VHDL 32 8

  2. osvvm-demo osvvm-demo Public

    A project demonstrating how to use the OSVVM library and its Axi4LiteManager verification component to simulate an airhdl register bank.

    VHDL 1

  3. scripts scripts Public

    A collection of airhdl-related scripts

    Python 1

  4. lfsr-example lfsr-example Public

    A PN9 sequence checker for the AD9645 analog-to-digital converter

    VHDL 2 1

Repositories

Showing 5 of 5 repositories
  • spi-to-axi-bridge Public

    An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

    VHDL 32 Apache-2.0 8 0 1 Updated Dec 6, 2023
  • lfsr-example Public

    A PN9 sequence checker for the AD9645 analog-to-digital converter

    VHDL 2 Apache-2.0 1 0 0 Updated Feb 27, 2023
  • scripts Public

    A collection of airhdl-related scripts

    Python 1 Apache-2.0 0 0 0 Updated Jan 25, 2023
  • .github Public
    0 0 0 0 Updated Jul 2, 2022
  • osvvm-demo Public

    A project demonstrating how to use the OSVVM library and its Axi4LiteManager verification component to simulate an airhdl register bank.

    VHDL 1 Apache-2.0 0 0 0 Updated Jun 19, 2022

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