Hardware prefetchers play an important role in hiding long data access latency in various multiprocessor systems. Significant number of prefetchers have been proposed using state-of-the-art techniques which independently augment the existing instruction pointer based and cache address based prefetching.
In this paper, we attempt to categorically evaluate the submissions of the Third Data Prefetching Championship (DPC3). Additionally, we also propose IPCP++, an enhanced version of Instruction Pointer Classifier based prefetcher (IPCP) reinforced with IP-Delta based sequence predictor and IP-based stride prefetcher (Sangam++). The confluence of these IP based prefetching techniques achieves a speedup of 9.39% over no prefetching when averaged over 20 single-thread 6XX SPEC CPU 2017 traces.
We also present a dynamic degree stream prefetcher. The dynamic stream prefetcher (DSP) takes into account factors like prefetch accuracy, cache pollution and strength of the stream in a given window of 1000 cycles to determine the prefetch degree dynamically.
This research work is done as a part of the Course Project for Advanced Computer Architecture (CS622A), Fall Semester - 2019, instructed by Prof. Mainak Chaudhury.
The simulation results for all the prefetchers are compiled here. And the project paper can be found here.
| Name | Roll | |
|---|---|---|
| Aditya Rohan | raditya@iitk.ac.in | 160053 |
| Aniket Pandey | aniketp@iitk.ac.in | 160113 |
- Install
champsimrepository
> cd scripts
> ./install-champsim.sh- Install DPC3 traces (SPEC 2017)
Either install the traces from within champsim repository in the project or
move already existing traces to champsim/dpc3_traces.
- Build CPU executables and run simulation on all prefetchers for all available traces.
> go run main.goNOTE If you already have built the CPUs using above command and introduced new traces for which you want to re-run the simulation, use
> go run main.go skip-cpuThis skips building the CPU executables again.