DDR

A simple DDR3 memory controller for Micron DDR3 RAM

Note:

1. This softcore IP had been verified (both functional and timing analysis) only inside Xilinx IDE.
2. It can reach an optimum fmax of 333.333MHz without STA timing violations, without the need of any external SDC.
3. I would only test this on actual development board once I got hold of it, so ignore any external SDC files I put in this repository for now.

TODO:

1. Implement more functionalities since the current verilog code does not yet support Additive Latency (AL), write-leveling mode, self-refresh mode, inserting other DRAM commands within write or read bursts data operation for a smarter DRAM controller
2. Implement Type-III digital PLL described in Floyd Gardner book: Phaselock Techniques, 3rd Edition for high-speed application and DQS phase-shift purpose
3. Investigate high-speed DDR PHY IO as described in reference [1], [2], [3], [4], [5], [6]
4. Design my own DDR3 FPGA board

Notes on Modelsim simulation for Micron DDR3 memory simulation model:

1. Creates a working directory named as ddr3 and copies ddr3_memory_controller.v, test_ddr3_memory_controller.v, 2048Mb_ddr3_parameters.vh, ddr3.v
2. Issues command : vsim -gui work._2048Mb_ddr3_parameters_vh_unit work.ddr3 work.ddr3_memory_controller work.ddr3_memory_controller_v_unit work.test_ddr3_memory_controller
3. Issues command : source modelsim_wave.do followed by run 710us
4. To restart simulation from timestep zero, just issue command : restart

Credit: @Elphel, @Morin, @Greg, @BrianHG and @NorthGuy for their helpful technical help and explanation

Reference:

[1]: Preamble detection and postamble closure for a memory interface controller

[2]: Circuit design technique for DQS enable/disable calibration

[3]: Dqs generating circuit in a ddr memory device and method of generating the dqs

[4]: DQS strobe centering (data eye training) method

[5]: Data strobe enable circuitry

[6]: Bimodal serial to parallel converter with bitslip controller