Merge pull request #39057 from lwang046/revert-timingbit

HcalDQM: Revert timing bit to old default, backport of #39058
cms-sw · Aug 23, 2022 · 4b13252 · 4b13252
2 parents 5668d98 + 0b5f736
commit 4b13252
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/DQM/HcalTasks/plugins/TPTask.cc b/DQM/HcalTasks/plugins/TPTask.cc
@@ -1130,7 +1130,9 @@ TPTask::TPTask(edm::ParameterSet const& ps)
       HcalElectronicsId const& eid(rawid);
 
       const bool HetAgreement = sentTp.SOI_compressedEt() == recdTp.SOI_compressedEt();
-      const bool Hfb1Agreement = sentTp.SOI_fineGrain() == recdTp.SOI_fineGrain();
+      const bool Hfb1Agreement =
+          (abs(ieta) < 29) ? true
+                           : (recdTp.SOI_compressedEt() == 0 || (sentTp.SOI_fineGrain() == recdTp.SOI_fineGrain()));
       // Ignore minBias (FB2) bit if we receieve 0 ET, which means it is likely zero-suppressed on HCal readout side
       const bool Hfb2Agreement =
           (abs(ieta) < 29) ? true