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@jbsauvan
jbsauvan committed Jul 23, 2021
1 parent 445233c commit 6c52b5b
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Showing 5 changed files with 44 additions and 30 deletions.
3 changes: 2 additions & 1 deletion DataFormats/ForwardDetId/interface/HGCalTriggerModuleDetId.h
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Expand Up @@ -35,7 +35,8 @@ class HGCalTriggerModuleDetId : public DetId {
/** Create module id from raw id (0=invalid id) */
HGCalTriggerModuleDetId(uint32_t rawid);
/** Constructor from subdetector, zplus, type, layer, sector, module numbers */
HGCalTriggerModuleDetId(HGCalTriggerSubdetector subdet, int zp, int type, int layer, int sector, int moduleU, int moduleV);
HGCalTriggerModuleDetId(
HGCalTriggerSubdetector subdet, int zp, int type, int layer, int sector, int moduleU, int moduleV);
/** Constructor from a generic det id */
HGCalTriggerModuleDetId(const DetId& id);
/** Assignment from a generic det id */
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7 changes: 4 additions & 3 deletions DataFormats/ForwardDetId/src/HGCalTriggerBackendDetId.cc
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Expand Up @@ -6,7 +6,8 @@ HGCalTriggerBackendDetId::HGCalTriggerBackendDetId() : DetId() {}

HGCalTriggerBackendDetId::HGCalTriggerBackendDetId(uint32_t rawid) : DetId(rawid) {}

HGCalTriggerBackendDetId::HGCalTriggerBackendDetId(int zp, int type, int sector, int label) : DetId(Forward, HGCTrigger) {
HGCalTriggerBackendDetId::HGCalTriggerBackendDetId(int zp, int type, int sector, int label)
: DetId(Forward, HGCTrigger) {
int classid = HGCalTriggerClassIdentifier::ModuleDetId;
int zside = (zp < 0) ? 1 : 0;
id_ |= (((label & kHGCalLabelMask) << kHGCalLabelOffset) | ((sector & kHGCalSectorMask) << kHGCalSectorOffset) |
Expand Down Expand Up @@ -36,7 +37,7 @@ HGCalTriggerBackendDetId& HGCalTriggerBackendDetId::operator=(const DetId& gen)
}

std::ostream& operator<<(std::ostream& s, const HGCalTriggerBackendDetId& id) {
return s << "HGCalTriggerBackendDetId::lpGBT:Stage1 FPGA:Stage2 FPGA= " << id.isLpGBT() << ":" << id.isStage1FPGA() << ":"
<< id.isStage1Link() << ":" << id.isStage2FPGA() << " z= " << id.zside() << " sector= " << id.sector()
return s << "HGCalTriggerBackendDetId::lpGBT:Stage1 FPGA:Stage2 FPGA= " << id.isLpGBT() << ":" << id.isStage1FPGA()
<< ":" << id.isStage1Link() << ":" << id.isStage2FPGA() << " z= " << id.zside() << " sector= " << id.sector()
<< " id= " << id.label();
}
7 changes: 4 additions & 3 deletions DataFormats/ForwardDetId/src/HGCalTriggerModuleDetId.cc
View file
Expand Up @@ -42,7 +42,8 @@ HGCalTriggerModuleDetId& HGCalTriggerModuleDetId::operator=(const DetId& gen) {
}

std::ostream& operator<<(std::ostream& s, const HGCalTriggerModuleDetId& id) {
return s << "HGCalTriggerModuleDetId::HFNose:EE:HSil:HScin= " << id.isHFNose() << ":" << id.isEE() << ":" << id.isHSilicon()
<< ":" << id.isHScintillator() << " type= " << id.type() << " z= " << id.zside() << " layer= " << id.layer()
<< " sector= " << id.sector() << " module(u,v)= (" << id.moduleU() << "," << id.moduleV() << ")";
return s << "HGCalTriggerModuleDetId::HFNose:EE:HSil:HScin= " << id.isHFNose() << ":" << id.isEE() << ":"
<< id.isHSilicon() << ":" << id.isHScintillator() << " type= " << id.type() << " z= " << id.zside()
<< " layer= " << id.layer() << " sector= " << id.sector() << " module(u,v)= (" << id.moduleU() << ","
<< id.moduleV() << ")";
}
53 changes: 32 additions & 21 deletions L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc
View file
Expand Up @@ -266,7 +266,8 @@ unsigned HGCalTriggerGeometryV9Imp3::getModuleFromTriggerCell(const unsigned tri
int ieta = ((trigger_cell_sc_id.ietaAbs() - ietamin_tc) / hSc_module_size_ + 1);
int iphi = (trigger_cell_sc_id.iphi() - 1) / hSc_module_size_ + 1;
unsigned sector = etaphiMappingToSector0(ieta, iphi);
module_id = HGCalTriggerModuleDetId(HGCalTriggerSubdetector::HGCalHScTrigger, zside, tc_type, layer, sector, ieta, iphi);
module_id =
HGCalTriggerModuleDetId(HGCalTriggerSubdetector::HGCalHScTrigger, zside, tc_type, layer, sector, ieta, iphi);
}
// HFNose
else if (det == DetId::HGCalTrigger and
Expand All @@ -279,7 +280,8 @@ unsigned HGCalTriggerGeometryV9Imp3::getModuleFromTriggerCell(const unsigned tri
int waferv = trigger_cell_trig_id.waferV();
unsigned sector = geom_rotation_120_.uvMappingToSector0(
getWaferCentring(layer, HGCalTriggerSubdetector::HFNoseTrigger), waferu, waferv);
module_id = HGCalTriggerModuleDetId(HGCalTriggerSubdetector::HFNoseTrigger, zside, tc_type, layer, sector, waferu, waferv);
module_id =
HGCalTriggerModuleDetId(HGCalTriggerSubdetector::HFNoseTrigger, zside, tc_type, layer, sector, waferu, waferv);
}
// Silicon
else {
Expand Down Expand Up @@ -577,11 +579,13 @@ HGCalTriggerGeometryBase::geom_set HGCalTriggerGeometryV9Imp3::getStage1LinksFro
auto stage2_itrs = stage2_to_stage1links_.equal_range(id.label());
for (auto stage2_itr = stage2_itrs.first; stage2_itr != stage2_itrs.second; stage2_itr++) {
if (stage2_itr->second == true) { //link and stage2 FPGA are the same sector
stage1link_ids.emplace(
HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1Link, id.sector(), stage2_itr->second));
} else { //link is from the next sector (anti-clockwise)
stage1link_ids.emplace(HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1Link, getNextSector(id.sector()), stage2_itr->second));
id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1Link, id.sector(), stage2_itr->second));
} else { //link is from the next sector (anti-clockwise)
stage1link_ids.emplace(HGCalTriggerBackendDetId(id.zside(),
HGCalTriggerBackendDetId::BackendType::Stage1Link,
getNextSector(id.sector()),
stage2_itr->second));
}
}

Expand All @@ -592,7 +596,8 @@ unsigned HGCalTriggerGeometryV9Imp3::getStage1FpgaFromStage1Link(const unsigned
HGCalTriggerBackendDetId id(link_id);
unsigned stage1_label = stage1link_to_stage1_.at(id.label());

return HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1FPGA, id.sector(), stage1_label);
return HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1FPGA, id.sector(), stage1_label);
}

unsigned HGCalTriggerGeometryV9Imp3::getStage2FpgaFromStage1Link(const unsigned link_id) const {
Expand All @@ -615,8 +620,8 @@ HGCalTriggerGeometryBase::geom_set HGCalTriggerGeometryV9Imp3::getStage1LinksFro

auto stage1_itrs = stage1_to_stage1links_.equal_range(id.label());
for (auto stage1_itr = stage1_itrs.first; stage1_itr != stage1_itrs.second; stage1_itr++) {
stage1link_ids.emplace(
HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1Link, id.sector(), stage1_itr->second));
stage1link_ids.emplace(HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1Link, id.sector(), stage1_itr->second));
}

return stage1link_ids;
Expand All @@ -628,8 +633,8 @@ HGCalTriggerGeometryBase::geom_set HGCalTriggerGeometryV9Imp3::getLpgbtsFromStag

auto stage1_itrs = stage1_to_lpgbts_.equal_range(id.label());
for (auto stage1_itr = stage1_itrs.first; stage1_itr != stage1_itrs.second; stage1_itr++) {
lpgbt_ids.emplace(
HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::LpGBT, id.sector(), stage1_itr->second));
lpgbt_ids.emplace(HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::LpGBT, id.sector(), stage1_itr->second));
}

return lpgbt_ids;
Expand All @@ -639,7 +644,8 @@ unsigned HGCalTriggerGeometryV9Imp3::getStage1FpgaFromLpgbt(const unsigned lpgbt
HGCalTriggerBackendDetId id(lpgbt_id);
unsigned stage1_label = lpgbt_to_stage1_.at(id.label());

return HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1FPGA, id.sector(), stage1_label);
return HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1FPGA, id.sector(), stage1_label);
}

HGCalTriggerGeometryBase::geom_set HGCalTriggerGeometryV9Imp3::getModulesFromLpgbt(const unsigned lpgbt_id) const {
Expand Down Expand Up @@ -670,8 +676,8 @@ HGCalTriggerGeometryBase::geom_set HGCalTriggerGeometryV9Imp3::getModulesFromLpg
}

int type = detIdWaferType(det, layer, moduleU, moduleV);
modules.emplace(
HGCalTriggerModuleDetId(HGCalTriggerSubdetector(subdet), id.zside(), type, layer, id.sector(), moduleU, moduleV));
modules.emplace(HGCalTriggerModuleDetId(
HGCalTriggerSubdetector(subdet), id.zside(), type, layer, id.sector(), moduleU, moduleV));
}

return modules;
Expand All @@ -684,8 +690,8 @@ HGCalTriggerGeometryV9Imp3::geom_set HGCalTriggerGeometryV9Imp3::getLpgbtsFromMo
auto module_itrs = module_to_lpgbts_.equal_range(
packLayerSubdetWaferId(id.layer(), id.triggerSubdetId(), id.moduleU(), id.moduleV()));
for (auto module_itr = module_itrs.first; module_itr != module_itrs.second; module_itr++) {
lpgbt_ids.emplace(
HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::LpGBT, id.sector(), module_itr->second));
lpgbt_ids.emplace(HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::LpGBT, id.sector(), module_itr->second));
}

return lpgbt_ids;
Expand All @@ -697,7 +703,8 @@ unsigned HGCalTriggerGeometryV9Imp3::getStage1FpgaFromModule(const unsigned modu
unsigned stage1_label =
module_to_stage1_.at(packLayerSubdetWaferId(id.layer(), id.triggerSubdetId(), id.moduleU(), id.moduleV()));

return HGCalTriggerBackendDetId(id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1FPGA, id.sector(), stage1_label);
return HGCalTriggerBackendDetId(
id.zside(), HGCalTriggerBackendDetId::BackendType::Stage1FPGA, id.sector(), stage1_label);
}

GlobalPoint HGCalTriggerGeometryV9Imp3::getTriggerCellPosition(const unsigned trigger_cell_det_id) const {
Expand Down Expand Up @@ -872,9 +879,12 @@ void HGCalTriggerGeometryV9Imp3::fillMaps() {
unsigned HGCalTriggerGeometryV9Imp3::packLayerSubdetWaferId(unsigned layer, int subdet, int waferU, int waferV) const {
unsigned packed_value = 0;

packed_value |= ((waferU & HGCalTriggerModuleDetId::kHGCalModuleUMask) << HGCalTriggerModuleDetId::kHGCalModuleUOffset);
packed_value |= ((waferV & HGCalTriggerModuleDetId::kHGCalModuleVMask) << HGCalTriggerModuleDetId::kHGCalModuleVOffset);
packed_value |= ((subdet & HGCalTriggerModuleDetId::kHGCalTriggerSubdetMask) << HGCalTriggerModuleDetId::kHGCalTriggerSubdetOffset);
packed_value |=
((waferU & HGCalTriggerModuleDetId::kHGCalModuleUMask) << HGCalTriggerModuleDetId::kHGCalModuleUOffset);
packed_value |=
((waferV & HGCalTriggerModuleDetId::kHGCalModuleVMask) << HGCalTriggerModuleDetId::kHGCalModuleVOffset);
packed_value |= ((subdet & HGCalTriggerModuleDetId::kHGCalTriggerSubdetMask)
<< HGCalTriggerModuleDetId::kHGCalTriggerSubdetOffset);
packed_value |= ((layer & HGCalTriggerModuleDetId::kHGCalLayerMask) << HGCalTriggerModuleDetId::kHGCalLayerOffset);
return packed_value;
}
Expand All @@ -883,7 +893,8 @@ void HGCalTriggerGeometryV9Imp3::unpackLayerSubdetWaferId(
unsigned wafer, unsigned& layer, int& subdet, int& waferU, int& waferV) const {
waferU = (wafer >> HGCalTriggerModuleDetId::kHGCalModuleUOffset) & HGCalTriggerModuleDetId::kHGCalModuleUMask;
waferV = (wafer >> HGCalTriggerModuleDetId::kHGCalModuleVOffset) & HGCalTriggerModuleDetId::kHGCalModuleVMask;
subdet = (wafer >> HGCalTriggerModuleDetId::kHGCalTriggerSubdetOffset) & HGCalTriggerModuleDetId::kHGCalTriggerSubdetMask;
subdet =
(wafer >> HGCalTriggerModuleDetId::kHGCalTriggerSubdetOffset) & HGCalTriggerModuleDetId::kHGCalTriggerSubdetMask;
layer = (wafer >> HGCalTriggerModuleDetId::kHGCalLayerOffset) & HGCalTriggerModuleDetId::kHGCalLayerMask;
}

Expand Down
4 changes: 2 additions & 2 deletions L1Trigger/L1THGCal/test/HGCalTriggerGeomTesterV9Imp3.cc
View file
Expand Up @@ -730,8 +730,8 @@ bool HGCalTriggerGeomTesterV9Imp3::checkMappingConsistency() {
for (auto stage1fpga : stage1fpgas) {
if (stage1FPGAs.find(stage1fpga) == stage1FPGAs.end()) {
edm::LogProblem("BadStage2") << "Error: \n Stage-1 FPGA " << stage1fpga << "("
<< HGCalTriggerBackendDetId(stage1fpga) << ")\n has not been found in \n stage-2 "
<< HGCalTriggerBackendDetId(stage2);
<< HGCalTriggerBackendDetId(stage1fpga)
<< ")\n has not been found in \n stage-2 " << HGCalTriggerBackendDetId(stage2);
std::stringstream output;
output << " Available Stage-1 FPGAs are:\n";
for (auto stage1FPGA : stage1FPGAs) {
Expand Down

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