Merge pull request #26549 from makortel/taskL1

Migrate L1 step to Tasks
cms-sw · May 2, 2019 · 8587c76 · 8587c76
2 parents 0c6c1d8 + 610818f
commit 8587c76
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Showing 30 changed files with 165 additions and 144 deletions.
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_CalouGT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_CalouGT_cff.py
@@ -122,7 +122,8 @@ def _print(ignored):
     )
 
 
-SimL1Emulator = cms.Sequence()
-stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackEmtf+unpackCsctf+unpackBmtf+unpackGtStage2
-                                 +SimL1EmulatorCore+packCaloStage2
-                                 +packGtStage2+rawDataCollector))
+SimL1EmulatorTask = cms.Task()
+stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackEmtf,unpackCsctf,unpackBmtf,unpackGtStage2
+                                 ,SimL1EmulatorCoreTask,packCaloStage2
+                                 ,packGtStage2,rawDataCollector))
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full2015Data_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full2015Data_cff.py
@@ -95,7 +95,8 @@ def _print(ignored):
     )
 
 
-SimL1Emulator = cms.Sequence()
-stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackDttf+unpackCsctf
-                                 +simHcalTriggerPrimitiveDigis+SimL1EmulatorCore+packCaloStage2
-                                 +packGmtStage2+packGtStage2+rawDataCollector))
+SimL1EmulatorTask = cms.Task()
+stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackDttf,unpackCsctf
+                                 ,simHcalTriggerPrimitiveDigis,SimL1EmulatorCoreTask,packCaloStage2
+                                 ,packGmtStage2,packGtStage2,rawDataCollector))
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullMC_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullMC_cff.py
@@ -101,16 +101,17 @@ def _print(ignored):
         ]
     )
 
-SimL1Emulator = cms.Sequence()
-stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackRPC
-                                                          + unpackDT
-                                                          + unpackCSC
-                                                          + unpackEcal
-                                                          + unpackHcal
-                                                          #+ simEcalTriggerPrimitiveDigis
-                                                          + simHcalTriggerPrimitiveDigis
-                                                          + SimL1EmulatorCore
-                                                          + packCaloStage2
-                                                          + packGmtStage2
-                                                          + packGtStage2
-                                                          + rawDataCollector))
+SimL1EmulatorTask = cms.Task()
+stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackRPC
+                                                          , unpackDT
+                                                          , unpackCSC
+                                                          , unpackEcal
+                                                          , unpackHcal
+                                                          #, simEcalTriggerPrimitiveDigis
+                                                          , simHcalTriggerPrimitiveDigis
+                                                          , SimL1EmulatorCoreTask
+                                                          , packCaloStage2
+                                                          , packGmtStage2
+                                                          , packGtStage2
+                                                          , rawDataCollector))
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullSimTP_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_FullSimTP_cff.py
@@ -113,9 +113,11 @@ def _print(ignored):
         ]
     )
 
-SimL1Emulator = cms.Sequence()
-stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackEmtf+unpackCsctf+unpackBmtf
-                                 +simEcalTriggerPrimitiveDigis
-                                 +simHcalTriggerPrimitiveDigis
-                                 +SimL1EmulatorCore+packCaloStage2
-                                 +packGmtStage2+packGtStage2+rawDataCollector))
+
+SimL1EmulatorTask = cms.Task()
+stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackEmtf,unpackCsctf,unpackBmtf
+                                 ,simEcalTriggerPrimitiveDigis
+                                 ,simHcalTriggerPrimitiveDigis
+                                 ,SimL1EmulatorCoreTask,packCaloStage2
+                                 ,packGmtStage2,packGtStage2,rawDataCollector))
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_Full_cff.py
@@ -151,10 +151,10 @@ def _print(ignored):
     )
 
 
-SimL1Emulator = cms.Sequence()
-stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackEcal+unpackHcal+unpackCSC+unpackDT+unpackRPC+unpackRPCTwinMux+unpackTwinMux+unpackOmtf+unpackEmtf+unpackCsctf+unpackBmtf
-                                                          +unpackLayer1
-                                                          +unpackTcds
-                                                          +SimL1EmulatorCore+packCaloStage2
-                                                          +packGmtStage2+packGtStage2+rawDataCollector))
-
+SimL1EmulatorTask = cms.Task()
+stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackEcal,unpackHcal,unpackCSC,unpackDT,unpackRPC,unpackRPCTwinMux,unpackTwinMux,unpackOmtf,unpackEmtf,unpackCsctf,unpackBmtf
+                                                          ,unpackLayer1
+                                                          ,unpackTcds
+                                                          ,SimL1EmulatorCoreTask,packCaloStage2
+                                                          ,packGmtStage2,packGtStage2,rawDataCollector))
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GCTGT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GCTGT_cff.py
@@ -93,14 +93,15 @@
 ## construct SimL1Emulator sequence
 ##
 
-SimL1Emulator = cms.Sequence(
-      unpackGtDigis      +
-      unpackCastorDigis  +
-      L1TCaloStage1_PPFromRaw +
-      newGtDigis         +
-      packGctDigis       +
-      packL1tDigis       +
-      packL1Gt           +
-      packL1GtEvm        +
+SimL1EmulatorTask = cms.Task(
+      unpackGtDigis      ,
+      unpackCastorDigis  ,
+      L1TCaloStage1_PPFromRawTask ,
+      newGtDigis         ,
+      packGctDigis       ,
+      packL1tDigis       ,
+      packL1Gt           ,
+      packL1GtEvm        ,
       rawDataCollector
 )
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT1_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT1_cff.py
@@ -67,12 +67,13 @@
 ## construct SimL1Emulator sequence
 ##
 
-SimL1Emulator = cms.Sequence(
-      unpackGctDigis     +
-      unpackGtDigis      +
-      unpackCastorDigis  +
-      newGtDigis         +
-      packL1Gt           +
-      packL1GtEvm        +
+SimL1EmulatorTask = cms.Task(
+      unpackGctDigis     ,
+      unpackGtDigis      ,
+      unpackCastorDigis  ,
+      newGtDigis         ,
+      packL1Gt           ,
+      packL1GtEvm        ,
       rawDataCollector
 )
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT2_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT2_cff.py
@@ -76,13 +76,14 @@
 ## construct SimL1Emulator sequence
 ##
 
-SimL1Emulator = cms.Sequence(
-      unpackGctStage1    +
-      unpackGctDigis     +
-      unpackGtDigis      +
-      unpackCastorDigis  +
-      newGtDigis         +
-      packL1Gt           +
-      packL1GtEvm        +
+SimL1EmulatorTask = cms.Task(
+      unpackGctStage1    ,
+      unpackGctDigis     ,
+      unpackGtDigis      ,
+      unpackCastorDigis  ,
+      newGtDigis         ,
+      packL1Gt           ,
+      packL1GtEvm        ,
       rawDataCollector
 )
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_GT_cff.py
@@ -61,13 +61,13 @@
     )
 )
 
-SimL1Emulator = cms.Sequence(
+SimL1EmulatorTask = cms.Task(
       unpackGctDigis
-    + unpackGtDigis
-    + unpackCastorDigis
-    + simGtDigis
-    + l1GtPack
-    + l1GtEvmPack
-    + rawDataCollector
+    , unpackGtDigis
+    , unpackCastorDigis
+    , simGtDigis
+    , l1GtPack
+    , l1GtEvmPack
+    , rawDataCollector
 )
-
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/Configuration/StandardSequences/python/SimL1EmulatorRepack_uGT_cff.py b/Configuration/StandardSequences/python/SimL1EmulatorRepack_uGT_cff.py
@@ -57,10 +57,11 @@ def _print(ignored):
     )
 
 
-SimL1Emulator = cms.Sequence()
-stage2L1Trigger.toReplaceWith(SimL1Emulator, cms.Sequence(unpackGtStage2
-                                                          +unpackTcds
-                                                          +SimL1TechnicalTriggers
-                                                          +SimL1TGlobal
-                                                          +packGtStage2
-                                                          +rawDataCollector))
+SimL1EmulatorTask = cms.Task()
+stage2L1Trigger.toReplaceWith(SimL1EmulatorTask, cms.Task(unpackGtStage2
+                                                          ,unpackTcds
+                                                          ,SimL1TechnicalTriggersTask
+                                                          ,SimL1TGlobalTask
+                                                          ,packGtStage2
+                                                          ,rawDataCollector))
+SimL1Emulator = cms.Sequence(SimL1EmulatorTask)
diff --git a/HLTrigger/Configuration/python/CustomConfigs.py b/HLTrigger/Configuration/python/CustomConfigs.py
@@ -146,7 +146,7 @@ def L1REPACK(process,sequence="Full"):
         getattr(process,path).insert(0,process.SimL1Emulator)
 
     # special L1T cleanup
-    for obj in ('SimL1TCalorimeter','SimL1TMuonCommon','SimL1TMuon','SimL1TechnicalTriggers','SimL1EmulatorCore','ecalDigiSequence','hcalDigiSequence','calDigi','me0TriggerPseudoDigiSequence','hgcalTriggerGeometryESProducer'):
+    for obj in ('SimL1TCalorimeter','SimL1TMuonCommon','SimL1TMuon','SimL1TechnicalTriggers','SimL1EmulatorCore','ecalDigiSequence','hcalDigiSequence','calDigi','me0TriggerPseudoDigiTask','hgcalTriggerGeometryESProducer'):
         if hasattr(process,obj):
             delattr(process,obj)
 

diff --git a/L1Trigger/Configuration/python/SimL1Emulator_cff.py b/L1Trigger/Configuration/python/SimL1Emulator_cff.py
@@ -37,14 +37,16 @@
 from L1Trigger.L1TGlobal.simDigis_cff import *
 
 # define a core which can be extented in customizations:
-SimL1EmulatorCore = cms.Sequence(
-    SimL1TCalorimeter +
-    SimL1TMuon +
-    SimL1TechnicalTriggers +
-    SimL1TGlobal
-    )
+SimL1EmulatorCoreTask = cms.Task(
+    SimL1TCalorimeterTask,
+    SimL1TMuonTask,
+    SimL1TechnicalTriggersTask,
+    SimL1TGlobalTask
+)
+SimL1EmulatorCore = cms.Sequence(SimL1EmulatorCoreTask)
 
-SimL1Emulator = cms.Sequence( SimL1EmulatorCore )
+SimL1EmulatorTask = cms.Task(SimL1EmulatorCoreTask)
+SimL1Emulator = cms.Sequence( SimL1EmulatorTask )
 
 # 
 # Emulators are configured from DB (GlobalTags)
@@ -58,9 +60,9 @@
 
 # Customisation for the phase2_hgcal era. Includes the HGCAL L1 trigger
 from  L1Trigger.L1THGCal.hgcalTriggerPrimitives_cff import *
-_phase2_siml1emulator = SimL1Emulator.copy()
-_phase2_siml1emulator += hgcalTriggerPrimitives
+_phase2_siml1emulator = SimL1EmulatorTask.copy()
+_phase2_siml1emulator.add(hgcalTriggerPrimitivesTask)
 
 from Configuration.Eras.Modifier_phase2_hgcal_cff import phase2_hgcal
 from Configuration.Eras.Modifier_phase2_hgcalV9_cff import phase2_hgcalV9
-phase2_hgcal.toReplaceWith( SimL1Emulator , _phase2_siml1emulator )
+phase2_hgcal.toReplaceWith( SimL1EmulatorTask , _phase2_siml1emulator )
diff --git a/L1Trigger/Configuration/python/SimL1TechnicalTriggers_cff.py b/L1Trigger/Configuration/python/SimL1TechnicalTriggers_cff.py
@@ -4,7 +4,8 @@
 import L1Trigger.L1TGlobal.simGtExtFakeProd_cfi
 simGtExtFakeStage2Digis = L1Trigger.L1TGlobal.simGtExtFakeProd_cfi.simGtExtFakeProd.clone()
 
-SimL1TechnicalTriggers = cms.Sequence(simGtExtFakeStage2Digis)
+SimL1TechnicalTriggersTask = cms.Task(simGtExtFakeStage2Digis)
+SimL1TechnicalTriggers = cms.Sequence(SimL1TechnicalTriggersTask)
 
 
 # BSC Technical Trigger
@@ -26,8 +27,8 @@
 simCastorTechTrigDigis = SimCalorimetry.CastorTechTrigProducer.castorTTRecord_cfi.simCastorTTRecord.clone()
 
 from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger
-(~stage2L1Trigger).toReplaceWith(SimL1TechnicalTriggers, cms.Sequence(
-        simBscDigis + 
-        simRpcTechTrigDigis + 
-        simHcalTechTrigDigis +
+(~stage2L1Trigger).toReplaceWith(SimL1TechnicalTriggersTask, cms.Task(
+        simBscDigis,
+        simRpcTechTrigDigis,
+        simHcalTechTrigDigis,
         simCastorTechTrigDigis ))
diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_PPFromRaw_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_PPFromRaw_cff.py
@@ -43,9 +43,10 @@
 
 
 # the sequence
-L1TCaloStage1_PPFromRaw = cms.Sequence(
+L1TCaloStage1_PPFromRawTask = cms.Task(
     L1TRerunHCALTP_FromRAW
-    +ecalDigis
-    +simRctDigis
-    +L1TCaloStage1
+    ,ecalDigis
+    ,simRctDigis
+    ,L1TCaloStage1Task
 )
+L1TCaloStage1_PPFromRaw = cms.Sequence(L1TCaloStage1_PPFromRawTask)
diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage1_cff.py
@@ -41,9 +41,10 @@
 0.952755905512,	0.96062992126,	0.968503937008,	0.976377952756,	0.984251968504,	0.992125984252,	1.0,
 )
 
-L1TCaloStage1 = cms.Sequence(
-    simRctUpgradeFormatDigis +
-    simCaloStage1Digis +
-    simCaloStage1FinalDigis +
+L1TCaloStage1Task = cms.Task(
+    simRctUpgradeFormatDigis,
+    simCaloStage1Digis,
+    simCaloStage1FinalDigis,
     simCaloStage1LegacyFormatDigis
 )
+L1TCaloStage1 = cms.Sequence(L1TCaloStage1Task)
diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_PPFromRaw_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_PPFromRaw_cff.py
@@ -10,7 +10,8 @@
 caloStage2Layer1Digis.hcalToken = cms.InputTag('simHcalTriggerPrimitiveDigis')
 
 # the sequence
-L1TCaloStage2_PPFromRaw = cms.Sequence(
+L1TCaloStage2_PPFromRawTask = cms.Task(
     L1TRerunHCALTP_FromRAW
-    +L1TCaloStage2
+    ,L1TCaloStage2Task
 )
+L1TCaloStage2_PPFromRaw = cms.Sequence(L1TCaloStage2_PPFromRawTask)
diff --git a/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_cff.py b/L1Trigger/L1TCalorimeter/python/L1TCaloStage2_cff.py
@@ -3,7 +3,8 @@
 from L1Trigger.L1TCalorimeter.caloStage2Layer1Digis_cfi import *
 from L1Trigger.L1TCalorimeter.caloStage2Digis_cfi import *
 
-L1TCaloStage2 = cms.Sequence(
+L1TCaloStage2Task = cms.Task(
     caloStage2Layer1Digis +
     caloStage2Digis
 )
+L1TCaloStage2 = cms.Sequence(L1TCaloStage2Task)
diff --git a/L1Trigger/L1TCalorimeter/python/L1TRerunHCALTP_FromRaw_cff.py b/L1Trigger/L1TCalorimeter/python/L1TRerunHCALTP_FromRaw_cff.py
@@ -10,7 +10,7 @@
 
 HcalTPGCoderULUT.LUTGenerationMode = cms.bool(True)
 
-L1TRerunHCALTP_FromRAW = cms.Sequence(
+L1TRerunHCALTP_FromRAW = cms.Task(
     hcalDigis
-    * simHcalTriggerPrimitiveDigis
+    , simHcalTriggerPrimitiveDigis
 )
diff --git a/L1Trigger/L1TCalorimeter/python/simDigis_cff.py b/L1Trigger/L1TCalorimeter/python/simDigis_cff.py
@@ -15,7 +15,8 @@
 simGctDigis = L1Trigger.GlobalCaloTrigger.gctDigis_cfi.gctDigis.clone(
     inputLabel = 'simRctDigis'
 )
-SimL1TCalorimeter = cms.Sequence(simRctDigis + simGctDigis)
+SimL1TCalorimeterTask = cms.Task(simRctDigis, simGctDigis)
+SimL1TCalorimeter = cms.Sequence(SimL1TCalorimeterTask)
 
 #
 # Stage-1 Trigger
@@ -30,7 +31,7 @@
 from L1Trigger.L1TCalorimeter.caloConfigStage1PP_cfi import *
 from Configuration.Eras.Modifier_stage1L1Trigger_cff import stage1L1Trigger
 from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger
-(stage1L1Trigger & ~stage2L1Trigger).toReplaceWith(SimL1TCalorimeter, cms.Sequence(simRctDigis + simRctUpgradeFormatDigis + simCaloStage1Digis + simCaloStage1FinalDigis + simCaloStage1LegacyFormatDigis))
+(stage1L1Trigger & ~stage2L1Trigger).toReplaceWith(SimL1TCalorimeterTask, cms.Task(simRctDigis, simRctUpgradeFormatDigis, simCaloStage1Digis, simCaloStage1FinalDigis, simCaloStage1LegacyFormatDigis))
 
 #
 # Stage-2 Trigger
@@ -41,7 +42,7 @@
 # - layer1 from L1Trigger/L1TCaloLayer1 package
 from L1Trigger.L1TCaloLayer1.simCaloStage2Layer1Digis_cfi import simCaloStage2Layer1Digis
 from L1Trigger.L1TCalorimeter.simCaloStage2Digis_cfi import simCaloStage2Digis
-stage2L1Trigger.toReplaceWith(SimL1TCalorimeter, cms.Sequence( simCaloStage2Layer1Digis + simCaloStage2Digis ))
+stage2L1Trigger.toReplaceWith(SimL1TCalorimeterTask, cms.Task( simCaloStage2Layer1Digis, simCaloStage2Digis ))
 
 def _modifyStage2L1TriggerCaloParams(process):
     from CondCore.CondDB.CondDB_cfi import CondDB

diff --git a/L1Trigger/L1TGlobal/python/simDigis_cff.py b/L1Trigger/L1TGlobal/python/simDigis_cff.py
@@ -22,7 +22,8 @@
         'simCastorTechTrigDigis'
     ]
 )
-SimL1TGlobal = cms.Sequence(simGtDigis)
+SimL1TGlobalTask = cms.Task(simGtDigis)
+SimL1TGlobal = cms.Sequence(SimL1TGlobalTask)
 
 #
 # Stage-2 Trigger
@@ -32,4 +33,4 @@
 #
 from L1Trigger.L1TGlobal.simGtStage2Digis_cfi import *
 from Configuration.Eras.Modifier_stage2L1Trigger_cff import stage2L1Trigger
-stage2L1Trigger.toReplaceWith(SimL1TGlobal, cms.Sequence(simGtStage2Digis))
+stage2L1Trigger.toReplaceWith(SimL1TGlobalTask, cms.Task(simGtStage2Digis))
diff --git a/L1Trigger/L1THGCal/python/hgcalBackEndLayer1_cff.py b/L1Trigger/L1THGCal/python/hgcalBackEndLayer1_cff.py
@@ -4,5 +4,5 @@
 from L1Trigger.L1THGCal.hgcalBackEndLayer1Producer_cfi import *
 
 
-hgcalBackEndLayer1 = cms.Sequence(hgcalBackEndLayer1Producer)
+hgcalBackEndLayer1 = cms.Task(hgcalBackEndLayer1Producer)
 
diff --git a/L1Trigger/L1THGCal/python/hgcalBackEndLayer2_cff.py b/L1Trigger/L1THGCal/python/hgcalBackEndLayer2_cff.py
@@ -4,5 +4,5 @@
 from L1Trigger.L1THGCal.hgcalBackEndLayer2Producer_cfi import *
 
 
-hgcalBackEndLayer2 = cms.Sequence(hgcalBackEndLayer2Producer)
+hgcalBackEndLayer2 = cms.Task(hgcalBackEndLayer2Producer)
 
diff --git a/L1Trigger/L1THGCal/python/hgcalConcentrator_cff.py b/L1Trigger/L1THGCal/python/hgcalConcentrator_cff.py
@@ -4,5 +4,5 @@
 from L1Trigger.L1THGCal.hgcalConcentratorProducer_cfi import *
 
 
-hgcalConcentrator = cms.Sequence(hgcalConcentratorProducer)
+hgcalConcentrator = cms.Task(hgcalConcentratorProducer)