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Address warning messages for low-quality 3-layer ALCTs in Phase2 WFs with 12_0_0_pre2 #34002
Address warning messages for low-quality 3-layer ALCTs in Phase2 WFs with 12_0_0_pre2 #34002
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+code-checks Logs: https://cmssdt.cern.ch/SDT/code-checks/cms-sw-PR-34002/23124
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A new Pull Request was created by @dildick (Sven Dildick) for master. It involves the following packages: L1Trigger/CSCTriggerPrimitives @cmsbuild, @rekovic, @cecilecaillol can you please review it and eventually sign? Thanks. cms-bot commands are listed here |
Please test |
+1 Summary: https://cmssdt.cern.ch/SDT/jenkins-artifacts/pull-request-integration/PR-13b145/15739/summary.html Comparison SummarySummary:
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Thanks @dildick for prompt fix. By the way, do you know why we can't capture this kind of warning from PR test? I assume it is there for a while. For example, I just look in the test result of another PR from a few days ago, |
+l1 |
This pull request is fully signed and it will be integrated in one of the next master IBs (tests are also fine). This pull request will now be reviewed by the release team before it's merged. @silviodonato, @dpiparo, @qliphy (and backports should be raised in the release meeting by the corresponding L2) |
+1 |
@srimanob. Not sure why. It might be that the one you looked at just did not happen to have such a low-quality ALCT in the ALCTDigiCollection. The ALCT from the muon (or from pileup) needs to be produced in a very specific part of the ME2/1 for the warning message to have appeared. |
PR description:
In issue #33993 @srimanob noted warning messages coming from the LCTQualityControl in Phase-2 workflows. Those are coming from 3-layer ALCTs in ME2/1 where we could match them to GE2/1 trigger primitives.
This idea was conceived several years ago for the Phase-2 muon upgrade. By lowering the layer threshold in ME2/1 to form an ALCT from 4 to 3, we could recover ALCT inefficiency in certain parts of the ME2/1 chamber where the high voltage is lowered. In the trigger path you could eliminate the pure 3-layer ALCT from the 3-layer ALCTs that have a matching GEM hit to enhance the quality. But in the DAQ path (readout) you would likely see a large increase in data transfer in Phase-2. Those DAQ rates are not well understood. Definitely not considering the new HGCal geometry which may increase ALCT rates in ME2/1. For that reason, it is probably better to increase the threshold for ALCTs in ME2/1 back to 4 (as it was before). It will give us a more realistic picture in the simulation - rather than hopes and dreams. What can be done in the future - something that would be worth studying - is a localized reduction of the threshold from 4 to 3 layers for patterns with wiregroups where the high voltage drops.
In the mean time, it is best to keep the threshold at 4 layers (even in scenarios with GEMs). The l1 single muon efficiency will drop slightly in the region 1.6 to 2.4 in phase-2 workflows.
If someone (in their private studies) would like to change it back to 3 layers, I made an improvement in
CSCUpgradeAnodeLCTProcessor ::getTempALCTQuality
so that the warning messages do not appear anymore. The low quality 3-layer ALCTs in ME2/1 when the GE2/1 would be assigned a quality of 1, just like 4-layer ALCTs.I also added more documentation on how the ghost cancellation works in the ALCT processor. This is something that will change slightly in the Run-3 emulation, i.e. more similar to the firmware than in Run-1 and Run-2.
PR validation:
In CMSSW_12_0_X_2021-06-06-2300 tested with
The last step produced the output
if this PR is a backport please specify the original PR and why you need to backport that PR:
N/A
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