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L1T phase-1: Fix OMTF input tags for Run 3 re-emulation workflow #34080

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merged 2 commits into from Jun 11, 2021
Merged

L1T phase-1: Fix OMTF input tags for Run 3 re-emulation workflow #34080

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6aee326
Changed OMTF inputs to fix missing muon in re-emulation
eyigitba Jun 2, 2021
a2620da
Changing OMTF DT inputs to simDtTriggerPrimitiveDigis and fixing simD…
eyigitba Jun 3, 2021
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11 changes: 10 additions & 1 deletion L1Trigger/Configuration/python/customiseReEmul.py
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Expand Up @@ -61,7 +61,7 @@ def L1TReEmulFromRAW2015(process):
cms.InputTag('hcalDigis')
)
process.L1TReEmul = cms.Sequence(process.simEcalTriggerPrimitiveDigis * process.simHcalTriggerPrimitiveDigis * process.SimL1Emulator)
process.simDtTriggerPrimitiveDigis.digiTag = 'muonDTDigis'
process.simDtTriggerPrimitiveDigis.digiTag = 'muonDTDigis'
process.simCscTriggerPrimitiveDigis.CSCComparatorDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCComparatorDigi')
process.simCscTriggerPrimitiveDigis.CSCWireDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCWireDigi' )

Expand Down Expand Up @@ -131,6 +131,7 @@ def L1TReEmulFromRAW2016(process):
cms.InputTag('hcalDigis'),
cms.InputTag('hcalDigis')
)
process.simDtTriggerPrimitiveDigis.digiTag = cms.InputTag("muonDTDigis")
process.simCscTriggerPrimitiveDigis.CSCComparatorDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCComparatorDigi')
process.simCscTriggerPrimitiveDigis.CSCWireDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCWireDigi' )
process.L1TReEmul = cms.Sequence(process.simEcalTriggerPrimitiveDigis * process.simHcalTriggerPrimitiveDigis * process.SimL1Emulator)
Expand Down Expand Up @@ -261,6 +262,14 @@ def L1TReEmulMCFromRAW(process):
L1TReEmulFromRAW(process)
stage2L1Trigger.toModify(process.simEmtfDigis, CSCInput = 'simCscTriggerPrimitiveDigis:MPCSORTED')
stage2L1Trigger.toModify(process.simOmtfDigis, srcCSC = 'simCscTriggerPrimitiveDigis:MPCSORTED')

# Temporary fix for OMTF inputs in MC re-emulation
run3_GEM.toModify(process.simOmtfDigis,
srcRPC = 'muonRPCDigis',
srcDTPh = 'simDtTriggerPrimitiveDigis',
srcDTTh = 'simDtTriggerPrimitiveDigis'
)

return process

def L1TReEmulMCFromRAWSimEcalTP(process):
Expand Down