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Update RelVal scripts #9349

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merged 5 commits into from Jun 5, 2015
Merged

Update RelVal scripts #9349

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b8cfcb1
add parameter to specify fastsim minibias for mixing for all workflow…
hengne May 28, 2015
5e16aad
update fullSim premixing samples
hengne May 30, 2015
2e379de
Merge branch 'CMSSW_7_4_X' into from-CMSSW_7_4_3-relval-forPR
hengne May 30, 2015
201776e
change Memory from 2400 to 3000
hengne May 30, 2015
8bcf2fd
apply the last commit, change Memory from 2400 to 3000.
hengne May 30, 2015
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2 changes: 1 addition & 1 deletion Configuration/PyReleaseValidation/python/MatrixInjector.py
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Expand Up @@ -105,7 +105,7 @@ def __init__(self,opt,mode='init',options=''):
"mergedLFNBase" : "/store/relval",
"dashboardActivity" : "relval",
"Multicore" : opt.nThreads,
"Memory" : 2400,
"Memory" : 3000,
"SizePerEvent" : 1234,
"TimePerEvent" : 1
}
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12 changes: 7 additions & 5 deletions Configuration/PyReleaseValidation/python/relval_steps.py
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Expand Up @@ -341,8 +341,9 @@ def identitySim(wf):
# THIS ABOVE IS NOT USED, AT THE MOMENT
'CMSSW_7_4_0_pre7-MCRUN2_74_V7-v1', # 3 - 13 TeV samples with GEN-SIM from 740_p6; also GEN-SIM-DIGI-RAW-HLTDEBUG for id tests
'CMSSW_7_3_0_pre1-PRE_LS172_V15_FastSim-v1', # 4 - fast sim GEN-SIM-DIGI-RAW-HLTDEBUG for id tests
'CMSSW_7_4_0_pre9_ROOT6-PU25ns_MCRUN2_74_V7-v1', # 6 - premix
'CMSSW_7_4_0_pre9_ROOT6-PU50ns_MCRUN2_74_V6-v1' # 7 - premix
'CMSSW_7_4_3-PU25ns_MCRUN2_74_V9-v9', # 5 - fullSim premix 25ns
'CMSSW_7_4_3-PU50ns_MCRUN2_74_V8-v9', # 6 - fullSim premix 50ns
'CMSSW_7_4_3-MCRUN2_74_V9_FastSim-v1' # 7 - fastSim minibias for mixing
]

# note: INPUT commands to be added once GEN-SIM w/ 13TeV+PostLS1Geo will be available
Expand Down Expand Up @@ -773,9 +774,10 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''):
PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} # temporary: one or a few releases as back-up
PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} # temporary: one or a few releases as back-up
PUFSAVE35={'--pileup':'GEN_AVE_35_BX_25ns'}
PUFSAVE10_DRMIX_ITO={'--pileup':'AVE_10_BX_25ns','--pileup_input':'das:/RelValMinBiasFS_13_ForMixing/CMSSW_7_4_0_pre9_ROOT6-MCRUN2_74_V7_FastSim-v1/GEN-SIM-RECO','--customise':'FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1'}
PUFSAVE35_DRMIX_ITO={'--pileup':'AVE_35_BX_25ns','--pileup_input':'das:/RelValMinBiasFS_13_ForMixing/CMSSW_7_4_0_pre9_ROOT6-MCRUN2_74_V7_FastSim-v1/GEN-SIM-RECO','--customise':'FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1'}
PUFS25={'--pileup':'AVE_35_BX_25ns','--pileup_input':'das:/RelValMinBiasFS_13_ForMixing/CMSSW_7_4_0_pre9_ROOT6-MCRUN2_74_V7_FastSim-v1/GEN-SIM-RECO'}
PUFSAVE10_DRMIX_ITO={'--pileup':'AVE_10_BX_25ns','--pileup_input':'das:/RelValMinBiasFS_13_ForMixing/%s/GEN-SIM-RECO'%(baseDataSetRelease[7],),'--customise':'FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1'}
PUFSAVE35_DRMIX_ITO={'--pileup':'AVE_35_BX_25ns','--pileup_input':'das:/RelValMinBiasFS_13_ForMixing/%s/GEN-SIM-RECO'%(baseDataSetRelease[7],),'--customise':'FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1'}
PUFS25={'--pileup':'AVE_35_BX_25ns','--pileup_input':'das:/RelValMinBiasFS_13_ForMixing/%s/GEN-SIM-RECO'%(baseDataSetRelease[7],)}


#
steps['TTbarFSPU']=merge([PUFS,Kby(100,500),steps['TTbarFS']] )
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