Electrical analysis

Electrical Analysis

Some notes from examining electrical characteristics of pins.

Procedure:

• Note ground pins GND while device off
• Note voltage of pins when device on
• Note resistance between pins and GND when device off
• Note resistance between pins and Vcc when device off, if Vcc pin is known

See notes in Embedded Analysis JTAG by hand section for expected pullups and resistance.

Reference

For copy+paste into project notes Dual row:

r2vcc r2gnd Volt         Volt r2gnd  r2vcc
                * 1   2 *                  
                * 3   4 *                  
                * 5   6 *                  
                * 7   8 *                  
                * 9  10 *                  
                * 11 12 *                  
                * 13 14 *                  
                * 15 16 *                  
                * 17 18 *                  
                * 19 20 *                  
(orientation: pin 1 nearest to..)

Single row:

      Volt  r2gnd  r2vcc
 1 *                   
 2 *                   
 3 *                   
 4 *                   
 5 *                   
 6 *                   
 7 *                   
 8 *                   
 9 *                   
10 *                   
11 *                   
12 *                   
(orientation: pin 1 nearerest to...)

Log

JTAG orientation success

Comparing the electrical characteristics of this target with a known common JTAG header layout found online gave us a few rules to make note of:

• Pin with lowest resistance to others was the VCC pin
• Pin with highest resistance was RESET pin
• 4 Pins with common 1k resistance to VCC were TDO/TDI/TMS/TCK.

It also broke certain assumtions:

• I assumed TDI would have a pull down resistor to GND, and it does not. This could be because JTAG on this target is disabled.