Skip to content

doonny/Vitis-In-Depth-Tutorial

 
 

Repository files navigation

Vitis™ In-Depth Tutorials


Unlocking a new design experience for all developers

The Vitis unified software platform enables the development of embedded software and accelerated applications on heterogeneous Xilinx platforms including FPGAs, SoCs, and Versal ACAPs. It provides a unified programming model for accelerating Edge, Cloud, and Hybrid computing applications.

Leverage integration with high-level frameworks, develop in C, C++, or Python using accelerated libraries or use RTL-based accelerators & low-level runtime APIs for more fine-grained control over implementation — Choose the level of abstraction you need.

Tutorials

The Vitis In-Depth Tutorials takes users through the design methodology and programming model for deploying accelerated application on all Xilinx platforms.

Start here! Learn the basics of the Vitis programming model by putting together your very first application. No experience necessary!

Learn how to use Vitis, Vitis-AI, and the Vitis accelerated libraries to implement a fully end-to-end accelerated application using purely software-defined flows - no hardware expertise required.

Use Vitis-AI to configure Xilinx hardware using the Tensorflow framework. Vitis-AI allows the user to quantize, compile, and deploy an inference model in a matter of minutes.

Learn how to use the Vitis core development kit to build, analyze, and optimize an accelerated algorithm developed in C++, OpenCL, and even low-level hardware description languages (HDLs) like Verilog and VHDL.

Learn how to use Vitis HLS, compiler, analyzer, and debugger to identify performance bottlenecks and make modifications to increase algorithm efficiency and performance using an Alveo card.

Learn how to build custom platforms for Vitis to target your own boards, and how to modify and extend existing platforms.

Learn how to configure the platform hardware sources, construct the runtime software environment, add support for software and hardware emulation, and more.

Learn how to optimize the CPU side of your application for efficient memory allocation, how to sequence system-level events, and more.

On the back-end, learn how to control Vitis system-level topologies and low-level hardware implementation.

Copyright© 2020 Xilinx

About

No description, website, or topics provided.

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages

  • C++ 67.5%
  • SystemVerilog 19.0%
  • C 5.5%
  • Tcl 2.5%
  • V 1.4%
  • Verilog 1.1%
  • Other 3.0%