Pinned

1. friscv friscv Public

   RISCV CPU implementation in SystemVerilog

   Coq 15 3

2. svut svut Public

   SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

   Python 61 14

3. bster bster Public

   Implementation of a binary search tree algorithm in a FPGA/ASIC IP

   SystemVerilog 12 3

4. async_fifo async_fifo Public

   A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

   Verilog 206 68

5. axi-crossbar axi-crossbar Public

   An AXI4 crossbar implementation in SystemVerilog

   SystemVerilog 86 23

6. svlogger svlogger Public

   SystemVerilog Logger

   SystemVerilog 15 1