- 🔭 I’m currently working on ASIC_VLSI
- 👨🏼🔬 I’m currently learning C/Python
- 👯 I’m looking to collaborate on ASIC_VLSI_Projects
- 🤔 Ask me about ASIC_VLSI
🎓
Studying
Currently pursuing Bachelor of Technology in Electronics and communication from GLA University Mathura. Skilled in Communication, Teamwork, VLSI Design, Cadence
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GLA University
- Mathura
-
03:29
(UTC +05:30) - ekanshban483@gmail.com
- in/ekansh-bansal-04ek122002
- @EkanshBansal5
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100DaysofRTL
100DaysofRTL Public"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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