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RFC: phy: restore operation at lower (50MHz) sys-clk-freq ci #69: Pull request #33 opened by gsomlo
May 19, 2024 01:32 1m 45s gsomlo:gls-fix-at-50MHz
gsomlo:gls-fix-at-50MHz
May 19, 2024 01:32 1m 45s
phy: Simplify Clk/CE generation. ci #68: Commit 1a3d474 pushed by enjoy-digital
May 13, 2024 14:27 1m 44s master
master
May 13, 2024 14:27 1m 44s
test/test_phy: Update. ci #67: Commit 6d8b004 pushed by enjoy-digital
May 13, 2024 13:53 1m 48s master
master
May 13, 2024 13:53 1m 48s
phy: Avoid Xilinx's specific BUFG and use synchronous logic to improv… ci #66: Commit 15bc2db pushed by enjoy-digital
May 13, 2024 12:57 1m 50s master
master
May 13, 2024 12:57 1m 50s
core: Improve cmd_argument/command timings. ci #65: Commit df059bf pushed by enjoy-digital
May 13, 2024 12:56 1m 39s cmd_timings
cmd_timings
May 13, 2024 12:56 1m 39s
gen.py: Export direction signals for controlling an external buffer ci #64: Pull request #32 opened by paulusmack
April 2, 2024 22:30 1m 59s paulusmack:master
paulusmack:master
April 2, 2024 22:30 1m 59s
setup.py: Add classifiers. ci #63: Commit 1e55953 pushed by enjoy-digital
January 1, 2024 14:31 1m 46s master
master
January 1, 2024 14:31 1m 46s
setup.py: Switch minimum Python version to 3.7 (To allow more than 25… ci #62: Commit c28d0e4 pushed by enjoy-digital
December 25, 2023 14:37 1m 45s 2023.12
2023.12
December 25, 2023 14:37 1m 45s
setup.py: Switch minimum Python version to 3.7 (To allow more than 25… ci #61: Commit c28d0e4 pushed by enjoy-digital
December 19, 2023 09:29 1m 48s master
master
December 19, 2023 09:29 1m 48s
setup.py: Improve indentation. ci #60: Commit d740ec5 pushed by enjoy-digital
December 19, 2023 09:05 1m 55s master
master
December 19, 2023 09:05 1m 55s
phy: Use BUFG on Xilinx devices to route clocker.ce to improve timings. ci #59: Commit 181c48b pushed by enjoy-digital
November 14, 2023 14:07 2m 27s master
master
November 14, 2023 14:07 2m 27s
CONTRIBUTORS: Update. ci #58: Commit 6072a55 pushed by enjoy-digital
November 10, 2023 09:47 1m 56s master
master
November 10, 2023 09:47 1m 56s
phy: Add buffers on SDPHYDATAW/R datapaths to improve timings. ci #57: Commit 8f15cbe pushed by enjoy-digital
November 7, 2023 15:55 2m 17s timing_improvements
timing_improvements
November 7, 2023 15:55 2m 17s
phy: Add buffers on SDPHYDATAW/R datapaths to improve timings. ci #56: Commit 8f15cbe pushed by enjoy-digital
November 7, 2023 15:20 2m 39s clocker_bufg
clocker_bufg
November 7, 2023 15:20 2m 39s
phy: Use BUFG on Xilinx devices to route clocker.ce to improve timings. ci #55: Commit 3c9b241 pushed by enjoy-digital
November 7, 2023 14:26 2m 50s clocker_bufg
clocker_bufg
November 7, 2023 14:26 2m 50s
Merge pull request #31 from gsomlo/gls-cmd-irq ci #54: Commit cf6ab89 pushed by enjoy-digital
October 5, 2023 06:23 2m 31s master
master
October 5, 2023 06:23 2m 31s
core: add edge-triggered irq signal for command completion ci #53: Pull request #31 opened by gsomlo
September 25, 2023 03:24 2m 12s gsomlo:gls-cmd-irq
gsomlo:gls-cmd-irq
September 25, 2023 03:24 2m 12s
phy: Update with LiteX improvements. ci #52: Commit e018257 pushed by enjoy-digital
September 14, 2023 08:49 2m 14s 2023.08
2023.08
September 14, 2023 08:49 2m 14s
phy: Update with LiteX improvements. ci #51: Commit e018257 pushed by enjoy-digital
July 26, 2023 14:30 2m 57s master
master
July 26, 2023 14:30 2m 57s
bench: Remove add_csr calls (no longer required). ci #50: Commit 15955d8 pushed by enjoy-digital
May 8, 2023 09:02 3m 4s 2023.04
2023.04
May 8, 2023 09:02 3m 4s