Datastorer

	flag 		== 0 if start of instructions 1 section
				== 1 if Belongs to instructions 1 section
				== 2 if end of instructions 1 section
				== 3 if start of instructions 2 section
				== 4 if Belongs to instructions 2 section
				== 5 if stop of instructions 2 section
				== 6 if start of Flags section
				== 7 if Belongs to Flags section
				== 8 if stop of Flags section
				== 9 if start of Data section
				== 10 if Belongs to Data section
				== 11 if stop of Data section
	data[0] 	== 0 if normal statement i.e. single node except ones discussed below
				== 1 if CMP // compare data[2] register with data[3] and store in currflag
				== 2 if SFG // compare and store in data[2] flag and add to flag section 
				== 3 if RSFG
				== 4 if ifstrtf
				== 5 if ifsf
				== 6 if elsestrtf
				== 7 if elsesf
				== 8 if whf
				== 9 if wfstrtf
				== 10 if wfsf
				== 11 if IfFG and True
				== 12 if IfFG and True
				== 13 if WhileFG and True
				== 14 if WhileFG and True
				== 15 if bck
				== 16 if Data storing note
	data[1]		== 0 if read						
				== 1 if write
				== 2 seek controller by 1
				== 3 seek controller by -1
				== 4 if create node after current and controller unchanged
				== 5 if create node before current and controller unchanged
				== 6 if delete node after current and controller unchanged
				== 7 if delete node before current and controller unchanged
				== 8 to move data from data[2] register to data[3] controller
				== 9 to move data to data[2] register from data[3] controller
				== 10 to move data from data[2] register to data[3] register

Syntax For assembly language (of lambda calculus simply bcz my machine lang is little readable)

	A list Storing a name 	== Variable
	/\ 						== lambda
	:= 						== Definition
	A list of Variables		== list
	.						== Simple dot used for abstraction
	()						== parenthesis used for application
	(						== LPAREN
	)						== RPAREN
	
Hereby let me give ISA specifications though in brief but the sole idea is here

I tried to have as minimal ISA as i could in this much time yet with little humanity too
So by stmt1 , stmt2 kind of statements assume it is going to be a single machine instruction .

Let us a program which operates sequentially , Without any if else

Ex. A program to add one node to Storage Memory after current location and then forward 
Storage memory pointer by 1 .

INST1s , stmt1 stmt2 | INST2s , | FLGS , | STRDT1 , STRDT2

=>	INST1s stmt1 , stmt2 | INST2s , | FLGS , | STRDT1 , DT1 STRDT2 

=>	INST1s stmt1 stmt2 , | INST2s , | FLGS , | STRDT1 DT1 , STRDT2 

Now Let us consider execution of a program with an if else . 

The 'C' kind of code (just to show blocks of code )

stmt1
if(exp1)
{
	stmt2
	stmt3
	if(exp2)
	{
		stmt4
		stmt5
	}
}
else
{
	stmt6
	stmt7
}


Sorry for this large example . But hope no one will shout about case handling atleast .
If you still think there is some where this will not work , then your warm welcome from me .

So let us see how it executes .

INST1s , stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s , | FLGS , | STRDT

=> INST1s stmt1 , CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s , | FLGS , | STRDT'

=> INST1s stmt1 CMP1 , SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s , | FLGS , | STRDT'

=> INST1s stmt1 CMP1 SFG1 , ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s , | FLGS FG1 , | STRDT'

=> INST1s stmt1 CMP1 SFG1 ifstrtf , stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf , | FLGS FG1 , | STRDT'

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 , stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf , | FLGS FG1 , | STRDT''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 , CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf , | FLGS FG1 , | STRDT'''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 , SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf , | FLGS FG1 , | STRDT'''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 , ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf , | FLGS FG1 FG2 , | STRDT'''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf , stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf ifstrtf , | FLGS FG1 FG2 , | STRDT'''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 , stmt5 ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf ifstrtf , | FLGS FG1 FG2 , | STRDT''''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 , ifsf elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf ifstrtf , | FLGS FG1 FG2 , | STRDT'''''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf , elstrtf stmt6 stmt7 ifelsf | INST2s ifstrtf , | FLGS FG1 , | STRDT'''''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf , stmt6 stmt7 ifelsf | INST2s elstrtf , | FLGS FG1 , | STRDT'''''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 , stmt7 ifelsf | INST2s elstrtf , | FLGS FG1 , | STRDT''''''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 , ifelsf | INST2s elstrtf , | FLGS FG1 , | STRDT'''''''

=> INST1s stmt1 CMP1 SFG1 ifstrtf stmt2 stmt3 CMP2 SFG2 ifstrtf stmt4 stmt5 ifsf elstrtf stmt6 stmt7 ifelsf , | INST2s , | FLGS , | STRDT'''''''









Now after vomiting out all this would you like to see for while too if you do then i will
show you just a simple version with nested while and after that with if else too

while(exp)
{
	stmt1
	stmt2
}

INST1s , CMP1 SFG1 whstrtf stmt1 stmt2 CMP1 RSFG1 whsf | INST2s , | FLGS , | STRDT

=> INST1s CMP1 , SFG1 whstrtf stmt1 stmt2 CMP1 RSFG1 whsf | INST2s , | FLGS , | STRDT

=> INST1s CMP1 SFG1 , whstrtf stmt1 stmt2 CMP1 RSFG1 whsf | INST2s , | FLGS FG1 , | STRDT

=> INST1s CMP1 SFG1 whstrtf , stmt1 stmt2 CMP1 RSFG1 whsf | INST2s whf whstrtf , | FLGS FG1 , | STRDT

=> INST1s CMP1 SFG1 whstrtf stmt1 , stmt2 CMP1 RSFG1 whsf | INST2s whf whstrtf bck, | FLGS FG1 , | STRDT'

=> INST1s CMP1 SFG1 whstrtf stmt1 stmt2 , CMP1 RSFG1 whsf | INST2s whf whstrtf bck bck, | FLGS FG1 , | STRDT''

=> INST1s CMP1 SFG1 whstrtf stmt1 stmt2 CMP1 , RSFG1 whsf | INST2s whf whstrtf bck bck bck , | FLGS FG1 , | STRDT''

=> INST1s CMP1 SFG1 whstrtf stmt1 stmt2 CMP1 RSFG1 , whsf | INST2s whf whstrtf bck bck bck bck , | FLGS FG1' , | STRDT''
	==> INST1s CMP1 SFG1 whstrtf , stmt1 stmt2 CMP1 RSFG1 whsf | INST2s whf whstrtf , | FLGS FG1' , | STRDT''
	==> INST1s CMP1 SFG1 whstrtf stmt1 stmt2 CMP1 RSFG1 whsf , | INST2s whf , | FLGS , | STRDT''
	
since if else is sequential and linear
above program works for if else too

Now let us consider nested while loop

while(exp1)
{
	stmt1
	while(exp2)
	{
		stmt2
	}
}

INST1s , CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s , | FLGS , | STRDT

=> INST1s CMP1 , SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s , | FLGS , | STRDT

=> INST1s CMP1 SF1 , whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s , | FLGS FG1 , | STRDT

=> INST1s CMP1 SF1 whstrtf , stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf , | FLGS FG1 , | STRDT

=> INST1s CMP1 SF1 whstrtf stmt1 , CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck , | FLGS FG1 , | STRDT'

=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 , SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck , | FLGS FG1 , | STRDT'

=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 , whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck , | FLGS FG1 , | STRDT'

=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf , stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf whstrtf , | FLGS FG1 FG2 , | STRDT'

=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 , CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf whstrtf bck , | FLGS FG1 FG2 , | STRDT''

=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 , RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf whstrtf bck bck , | FLGS FG1 FG2 , | STRDT''

=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 , whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf whstrtf bck bck bck , | FLGS FG1 FG2' , | STRDT''



N=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf , CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf , | FLGS FG1 , | STRDT''

N=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 , RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf bck , | FLGS FG1 , | STRDT''

N=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 , whsf | INST2s whf wfstrtf bck bck bck whf bck bck , | FLGS FG1' , | STRDT''

NN=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf , | INST2s whf , | FLGS , | STRDT''

NY=> INST1s CMP1 SF1 whstrtf , stmt1 CMP2 SF2 whstrtf stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf whstrtf , | FLGS FG' , | STRDT''

Y=> INST1s CMP1 SF1 whstrtf stmt1 CMP2 SF2 whstrtf , stmt2 CMP2 RSFG2 whsf CMP1 RSFG1 whsf | INST2s whf wfstrtf bck bck bck whf whstrtf , | FLGS FG1 FG2' , | STRDT''



after all this job i have only one thing to say

With Regards
HCKKID