ChiBench consists of a large collection of Verilog programs mined from open-source github repositories. The goal of this benchmark suite is to test and debug electronic design automation (EDA) tools, such as the Jasper Formal Verification Platform or Intel Quartus. To test your EDA tool, simply pass all the programs in the ChiBench collection to it, and see if it crashes. Below we list two examples of issues reported in this way:
- 2159: Verible's obfuscator crashes when reading a program that only contains the pragma directive.
- 2181: Verible's parser crashes instead of reporting syntax errors related to instantiation type.
ChiBench contains only programs that were originally distributed with some license. Thus, each program in the ChiBench suite contains, as a header comment, the original license of that specification, plus a link to the repository from where that code was obtained. Notice that these programs might use different licenses, given that they were extracted from different projects. On May 24th, 2024, the following licenses were used among the repositories mined to build the ChiBench collection:
| License | # |
|---|---|
| Apache License 2.0 | 341 |
| MIT License | 331 |
| GNU General Public License v3.0 | 159 |
| GNU General Public License v2.0 | 37 |
| BSD 3-Clause "New" or "Revised" License | 37 |
| BSD 2-Clause "Simplified" License | 27 |
| GNU Lesser General Public License v2.1 | 10 |
| Creative Commons Zero v1.0 Universal | 9 |
| The Unlicense | 7 |
| GNU Lesser General Public License v3.0 | 5 |
| Mozilla Public License 2.0 | 5 |
| ISC License | 5 |
| Creative Commons Attribution Share Alike 4.0 International | 4 |
| CERN Open Hardware Licence Version 2 - Permissive | 3 |
| GNU Affero General Public License v3.0 | 3 |
| Creative Commons Attribution 4.0 International | 2 |
| CERN Open Hardware Licence Version 2 - Strongly Reciprocal | 1 |
| CERN Open Hardware Licence Version 2 - Weakly Reciprocal | 1 |
This project is sponsored by Cadence Design Systems. Additionally, the different people involved in this project acknowledge the support of CNPq, FAPEMIG, and CAPES. Finally, thank UFMG's Department of Computer Science for making available the infrastructure necessary to carry out this project.