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Remove the IA-64 backend.
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llvm-svn: 76920
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Dan Gohman committed Jul 24, 2009
1 parent cdd405d commit 1715115
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Showing 53 changed files with 13 additions and 4,544 deletions.
1 change: 0 additions & 1 deletion llvm/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,6 @@ set(LLVM_ALL_TARGETS
CBackend
CellSPU
CppBackend
IA64
Mips
MSIL
MSP430
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63 changes: 0 additions & 63 deletions llvm/Xcode/LLVM.xcodeproj/project.pbxproj
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Expand Up @@ -255,8 +255,6 @@
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Expand Down Expand Up @@ -315,7 +313,6 @@
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Expand Down Expand Up @@ -415,13 +412,6 @@
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Expand Down Expand Up @@ -450,9 +440,6 @@
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Expand Down Expand Up @@ -682,20 +669,6 @@
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Expand Down Expand Up @@ -1830,7 +1803,6 @@
DE66EE9708ABEE5D00323D32 /* Alpha */,
CF8F1BCF0B64FC8A00BB4199 /* ARM */,
DE66EEC908ABEE5E00323D32 /* CBackend */,
DE66EEE508ABEE5E00323D32 /* IA64 */,
9F7794120C73CB6100551F9C /* Mips */,
DE66EF1108ABEE5E00323D32 /* PowerPC */,
DE66EF7008ABEE5F00323D32 /* Sparc */,
Expand Down Expand Up @@ -1906,41 +1878,6 @@
path = CBackend;
sourceTree = "<group>";
};
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CFA702C90A6FA8910006009A /* IA64GenRegisterInfo.inc */,
CFA702CA0A6FA8910006009A /* IA64GenRegisterNames.inc */,
DE66EEF808ABEE5E00323D32 /* IA64.h */,
DE66EEF908ABEE5E00323D32 /* IA64.td */,
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Expand Down
6 changes: 1 addition & 5 deletions llvm/autoconf/configure.ac
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Original file line number Diff line number Diff line change
Expand Up @@ -221,7 +221,6 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
alpha*-*) llvm_cv_target_arch="Alpha" ;;
ia64-*) llvm_cv_target_arch="IA64" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
pic16-*) llvm_cv_target_arch="PIC16" ;;
Expand Down Expand Up @@ -347,7 +346,6 @@ else
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
Alpha) AC_SUBST(TARGET_HAS_JIT,1) ;;
IA64) AC_SUBST(TARGET_HAS_JIT,0) ;;
ARM) AC_SUBST(TARGET_HAS_JIT,0) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,0) ;;
PIC16) AC_SUBST(TARGET_HAS_JIT,0) ;;
Expand Down Expand Up @@ -403,15 +401,14 @@ AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all,host-only,{target-name} (default=all)]),,
enableval=all)
case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU PIC16 XCore MSP430 SystemZ CBackend MSIL CppBackend" ;;
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ CBackend MSIL CppBackend" ;;
host-only)
case "$llvm_cv_target_arch" in
x86) TARGETS_TO_BUILD="X86" ;;
x86_64) TARGETS_TO_BUILD="X86" ;;
Sparc) TARGETS_TO_BUILD="Sparc" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC" ;;
Alpha) TARGETS_TO_BUILD="Alpha" ;;
IA64) TARGETS_TO_BUILD="IA64" ;;
ARM) TARGETS_TO_BUILD="ARM" ;;
Mips) TARGETS_TO_BUILD="Mips" ;;
CellSPU|SPU) TARGETS_TO_BUILD="CellSPU" ;;
Expand All @@ -429,7 +426,6 @@ case "$enableval" in
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ia64) TARGETS_TO_BUILD="IA64 $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
Expand Down
2 changes: 0 additions & 2 deletions llvm/cmake/config-ix.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,6 @@ elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
set(LLVM_NATIVE_ARCH PowerPC)
elseif (LLVM_NATIVE_ARCH MATCHES "alpha")
set(LLVM_NATIVE_ARCH Alpha)
elseif (LLVM_NATIVE_ARCH MATCHES "ia64")
set(LLVM_NATIVE_ARCH IA64)
elseif (LLVM_NATIVE_ARCH MATCHES "arm")
set(LLVM_NATIVE_ARCH ARM)
elseif (LLVM_NATIVE_ARCH MATCHES "mips")
Expand Down
3 changes: 0 additions & 3 deletions llvm/cmake/modules/LLVMConfig.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -148,9 +148,6 @@ set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMSys
set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMDebugger LLVMAnalysis LLVMBitReader LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMIA64AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMIA64Info LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMIA64CodeGen LLVMCodeGen LLVMCore LLVMIA64Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMIA64Info LLVMSupport)
set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget)
Expand Down
7 changes: 1 addition & 6 deletions llvm/configure
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Original file line number Diff line number Diff line change
Expand Up @@ -2400,7 +2400,6 @@ else
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
alpha*-*) llvm_cv_target_arch="Alpha" ;;
ia64-*) llvm_cv_target_arch="IA64" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
pic16-*) llvm_cv_target_arch="PIC16" ;;
Expand Down Expand Up @@ -4842,8 +4841,6 @@ else
x86_64) TARGET_HAS_JIT=1
;;
Alpha) TARGET_HAS_JIT=1
;;
IA64) TARGET_HAS_JIT=0
;;
ARM) TARGET_HAS_JIT=0
;;
Expand Down Expand Up @@ -4938,15 +4935,14 @@ else
fi

case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU PIC16 XCore MSP430 SystemZ CBackend MSIL CppBackend" ;;
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ CBackend MSIL CppBackend" ;;
host-only)
case "$llvm_cv_target_arch" in
x86) TARGETS_TO_BUILD="X86" ;;
x86_64) TARGETS_TO_BUILD="X86" ;;
Sparc) TARGETS_TO_BUILD="Sparc" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC" ;;
Alpha) TARGETS_TO_BUILD="Alpha" ;;
IA64) TARGETS_TO_BUILD="IA64" ;;
ARM) TARGETS_TO_BUILD="ARM" ;;
Mips) TARGETS_TO_BUILD="Mips" ;;
CellSPU|SPU) TARGETS_TO_BUILD="CellSPU" ;;
Expand All @@ -4966,7 +4962,6 @@ echo "$as_me: error: Can not set target to build" >&2;}
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ia64) TARGETS_TO_BUILD="IA64 $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
Expand Down
6 changes: 3 additions & 3 deletions llvm/docs/CodeGenerator.html
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Original file line number Diff line number Diff line change
Expand Up @@ -1380,9 +1380,9 @@
for <tt>RegisterClass</tt>, the last parameter of which is a list of
registers. Just commenting some out is one simple way to avoid them being
used. A more polite way is to explicitly exclude some registers from
the <i>allocation order</i>. See the definition of the <tt>GR</tt> register
class in <tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
</p>

<p>Virtual registers are also denoted by integer numbers. Contrary to physical
registers, different virtual registers never share the same number. The
Expand Down

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