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C64 SID problems. #18
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The SID of the TC64 core sounds exactly like the real thing to my ears. Unfortunately it isn't open-source...
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Not open source is useless here. Did you try Hollywood Poker Pro Intro on TC64? https://www.youtube.com/watch?v=mn4pGa5nIR4 |
May be i will tell crazy thought, but what if.... make some core with high enough CPU clock and run VICE inside it? Because VICE looks very polished and mature comparing to FPGA64. And it looks like nobody works on code anymore. |
Does vice run fast and accurate enough on the amiga 500 or the Atari ST? That's about the fastest we have on the mist today. It might be possible but instead of writing a whole c64 in hdl you'd write a complete system able to run the vice emulator. I'd assume that might even be more work. |
There is another c64 core which is also named fpga64: http://fpga64.blogspot.de I once was in contact with him but haven't received in answer for over a year. That core is lacking floppy support which we now have. It would imho make much more sense to get in touch with him again. |
In the mean time i've got more ideas. |
About that FPGA64 project: i've found the sources used in project here https://svn.pacedev.net/repos/pace/sw/src/component/sound/sid/ It uses the same SID model as MIST. |
Ah, indeed. Too bad. But the rest seems pretty cool and may be worth a look, anyway. |
On the subject of systems fast enough to run VICE, the f32c MIPS/RISCV core is interesting - in MIPS configuration the CPU is significantly smaller than the TG68 but it's ridiculously fast - it can turn in about 180DMIPS @ 100MHz. |
Hmm. Tried to register on fpgaarcade forum but got rejection (and it seems manual admin approval). It seems not everyone allowed to be there. |
Be careful with code from fpgaarcade.com - AFAIKat least some code there is only allowed to be used on the fpga arcade board, so it's not really open-source, or at least not GPL - compatible. As for running VICE on MiST, my guess is that this emulator is way too complex, so it would be really hard to run it full speed on any CPU architecture. BTW, I have a Pentium 200 system with 133MHz SDRAM, which I guess is surely above the maximum performance one could get from a Cyclone III FPGA, I'll try to run Vice on it and see if it works normally. |
SID code doesn't limit usage on fpgaarcade board only. No GPL mention but free to use and redistribute. Anyway, the code is also not working well. |
Hi. sorgelig, I have no idea why you got rejected, please email and I'll fix it. The forum is getting a huge amount of spammer registrations and this was a necessary step. I posted some comments apologizing for this and asking anybody who did not receive a mail to contact me. I intend to look at the SID filters again shortly. |
Mike: OK. sorgelig: maybe it is a better idea to check the SwinSID code and see if we can fix the current SID implementation, instead of replacing it with a ATMega core and related code - it just seems simpler to do. I can check the noise channel implementation - I guess this is a simple LFSR pseudo-random noise generator, so all that is required is figuring out what kind of polynomial is used, and the initial state. |
@fpgaaracde Mike, glad to see you here! My mailbox name is very suspicious, right :) It's because i've made it long time ago just for registering on boards and eventually receive the spam. When i registered on github i didn't expect to participate in development, but it turned out i'm in. My mailbox is pour.garbage_at_gmail.com I've tried to mail to admin of board without success. That's good, you will continue your SID library. Additional to Noise, there is something strange with channels. Hollywood Poker Pro(HPP) Intro looks like one channel is missing. I have your SID library integrated into C64 code. If you want, i can send you the code for testing. @rkrajnc I've learned how to implement true RNG using LFSR with cell ring oscillator while working on Menu core. So, may be it can be used in SID. |
@sorgelig, Which mail address did you sent to, I received nothing (which is On 18/01/2016 08:13, sorgelig wrote:
This email has been checked for viruses by Avast antivirus software. |
@fpgaaracde |
Hi, @fpgaaracde https://github.com/fpgaaracde
"modifed by XXX, original at svn.fpgaarcade.com" and your changes. I'll merge back any fixes. Why wouldn't clocking the code at 32MHz with a 1M clock enable work with This email has been checked for viruses by Avast antivirus software. |
Why don't you want to upload repository to github? About clocking: for 32MHz i have to create 1MHz EN strobe. I've tried to make it but failed. So, to make task easier i've just made 2 clocks separate. Especially because of sound problems i wanted to minimize incompatibilities in clocking. |
This has been discussed on the forum. Several reasons, the main one is On 18/01/2016 13:45, sorgelig wrote:
This email has been checked for viruses by Avast antivirus software. |
The SID code in C64 core doesn't look accurate. Sound in some tunes looks strange or messed in some cases.
For example, Intro with dancing girl (again dancing girl, haha!) in Hollywood Poker Pro is very messed.
And even tunes primarily considered OK, sound strange. Turrican II Title sound is too jerky...
One problem in SID code is noise generator. The second is total filter absence in code.
I've found another, unfortunately unfinished, SID FPGA project in fpgaarcade forum. That project is based on chip decaping according to author. I've made it work with C64 core, it also has issues, but what is working, looks correct. It seems like one channel is not working, and i didn't find the source of problem. But noise does look correct. It also has filters implementation, but according to author the filter part hasn't finished yet. I've imported noise generator to existing SID code from fpgaarcade project. Noise is better, but not enough to be acceptable.
Does anyone now other FPGA SID implementations? Or may be someone can help to fix the problems by mixing these 2 SID implementations?
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