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Dhrystone results

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ict edited this page Jan 3, 2022 · 18 revisions

This page stores various results obtained from running the Dhrystone benchmark included in this package. Bold text indicates the best result from a given compiler.

Due to Dhrystone's apparent inefficacy on more recent hardware, this page isn't often updated with new systems.

Jump to: Embedded Systems, Workstations, Servers

Embedded Systems

HP t5325

The t5325 is a miniscule low-power thin client unveiled by HP in late 2009, designed around a Marvell Kirkwood 88F6281 system-on-a-chip implementing a Marvell designed ARMv5TE-compliant "Sheeva" processor core clocked at 1.2 GHz with independent 16 KiB instruction and data caches and a 256 KiB unified secondary cache. All tests are performed under the HP "ThinPro" operating system, a lightly customized variant of Debian Lenny, on a system not specifically configured for benchmarking.

GCC 4.2.4: 10,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 714,285.7 406.5
-O1 1,428,571.4 813.1
-O2 1,428,571.4 813.1
-O3 1,666,666.7 948.6
-O3 -ffast-math 1,666,666.7 948.6

GCC 4.2.4: 10,000,000 loops, with register variables

Options Dhrystones/second VAX MIPS
none 769,230.8 437.8
-O1 1,250,000 711.4
-O2 1,250,000 711.4
-O3 1,428,571.4 813.1
-O3 -ffast-math 1,428,571.4 813.1

I-O DATA USL-5P

No data is available for -O1 due to a compiler bug interfering with register allocation.

GCC 4.2.1: 10,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 158,730.2 90.3
-O1 N/A N/A
-O2 277,777.8 158.1
-O3 333,333.3 189.7

GCC 4.2.1: 10,000,000 loops, with register variables

Options Dhrystones/second VAX MIPS
none 169,491.5 96.5
-O1 N/A N/A
-O2 285,714.3 162.6
-O3 344,827.6 196.3

Workstations

The mid-range offering of Apple's final generation of PowerPC-based professional systems, the 2.3DC was introduced in October 2005 and was designed around IBM's new dual-core 64-bit PowerPC 970MP processor, which featured two PowerPC 970 cores each with 32 KiB data cache, 64 KiB instruction cache, and a unified 1 MiB secondary cache, all running at a clock frequency of 2.3 GHz. The 970MP is interfaced to an off-chip DDR2 memory controller by a 1.15 GHz, 64-bit data bus composed of two separate 32-bit uni-directional buses. This system is outfitted with 8 GiB of error-correcting DDR2 memory clocked at 266 MHz (with an effective 533 MT/s data rate.)

All tests are performed under Mac OS 10.4.11, on a system not specifically configured for benchmarking.

Apple GCC 4.0.1: 50,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 1,515,151.5 862.4
-O1 4,545,454.5 2587.1
-O2 5,000,000.0 2,845.8
-O3 6,250,000.0 3,557.2

Apple GCC 4.0.1: 50,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 1,612,903.2 918.0
-O1 5,000,000.0 2,845.8
-O2 5,000,000.0 2,845.8
-O3 7,142,857.1 4,065.4

HP VISUALIZE C3000 (9000/785/C3000)

A mid-range Unix workstation released in 1999, based on HP's indigenous PA-8500 microprocessor with 1 MiB of on-die data cache, 512 KiB of on-die instruction cache and a clock frequency of 400 MHz. All tests are performed under HP-UX 11.11 (11i v1) on a system not specifically configured for benchmarking, using time() for timing and with an HZ value of 100.

The differences in performance between Dhrystone run with and without register variables is minimal, likely due to the PA-8500's large number of general-purpose registers (32 general-purpose and 32 floating-point) and fast, spacious on-die caches.

HP C B.11.11.16: 50,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 442,477.9 251.8
+O1 666,666.7 379.4
+O2 1,000,000 569.2
+O3 1,282,051.3 729.7
+O4 1,851,851.9 1,054
-fast 1,470,588.2 837

HP C B.11.11.16: 50,000,000 loops, with register variables

Options Dhrystones/second VAX MIPS
none 495,049.5 281.8
+O1 657,894.7 374.4
+O2 1,000,000 569.2
+O3 1,282,051.3 729.7
+O4 1,785,714.3 1,016.3
-fast 1,470,588.2 837

Note: HP C +O2 is roughly equivalent to GCC -O1

GCC 4.2.3: 50,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 431,034.5 245.3
-O1 806,451.6 459
-O2 833,333.3 474.3
-O3 1,136,363.6 646.8
-O3 -ffast-math 1,136,363.6 646.8

GCC 4.2.3: 50,000,000 loops, with register variables

Options Dhrystones/second VAX MIPS
none 438,596.5 249.6
-O1 781,250.0 444.6
-O2 806,451.6 459
-O3 1,162,790.7 661.8
-O3 -ffast-math 1,162,790.7 661.8

Note: -Ofast is only available in GCC >=4.7

Servers

Sun Fire T1000

The Sun Fire T1000 is an entry-level 1U rackmounted server released in early 2006 as one of the first systems to use Sun's radically multi-threaded UltraSPARC T1 "Niagra" microprocessor, derived from a SPARC implementation originally developed by Afara Websystems that features four, six or eight relatively simple SPARC V9 cores with individual 16 KiB instruction caches and 8 KiB data caches, a shared 3 MiB secondary cache and a single floating-point unit shared among all cores. Each core also has four threads, all sharing a single pipeline and a massive register file composed of 640 64-bit registers that allows for a thread's state to be quickly saved and resumed in a single cycle in order to maximize processor utilization in heavily multi-threaded workloads. The T1 utilized in the T1000 is clocked at 1 GHz.

All tests are performed on a T1000 with an 8-core UltraSPARC T1 running Solaris 10 10/09 with no specific configuration for benchmarking purposes. Because Dhrystone does not support multiple threads/processors, all results are for execution on one thread only. Keep this in mind when interpreting these results, as the T1's single-thread performance can be incredibly weak.

Sun Studio 12/Sun C 5.9: 10,000,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 625,000 355.7
-xO1 370,370.4 210.8
-xO2 833,333.3 474.3
-xO3 909,090.9 517.4
-xO4 909,090.9 517.4
-xO5 1,000,000 569.2
-fast 909,090.9 517.4

Sun Studio 12/Sun C 5.9: 10,000,000 loops, with register variables

Options Dhrystones/second VAX MIPS
none 666,666.7 379.4
-xO1 357,142.9 203.3
-xO2 909,090.9 517.4
-xO3 833,333.3 474.3
-xO4 1,000,000 569.2
-xO5 909,090.9 517.4
-fast 909,090.9 517.4

GCC 5.5.0: 20,000 loops, without register variables

Options Dhrystones/second VAX MIPS
none 434,782.6 247.5
-O1 909,090.9 517.4
-O2 1,000,000 569.2
-O3 1,000,000 569.2
-Ofast 1,000,000 569.2

GCC 5.5.0: 20,000 loops, with register variables

Options Dhrystones/second VAX MIPS
none 500,000 284.6
-O1 909,090.9 517.4
-O2 1,000,000 569.2
-O3 1,000,000 569.2
-Ofast 1,000,000 569.2
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