Frost is a simple RISC-V CPU implemented in Verilog. It is written assuming that it will be synthesised for an FPGA using the open source tools Yosys, nextpnr, etc.
I'm working on this as way of practising Verilog and learning something about RISC-V, so you almost certainly don't want it as a dependency in your project -- there are more suitable cores available elsewhere.
Feedback of any kind would be very welcome! You can find my email on my homepage.
- The base RV32I module is implemented. The corresponding riscv-tests pass.
- Instructions take between 3 and 6 cycles to execute. There is no pipelining.
- Unaligned memory reads are not supported. They don't trap either, so there's no way to handle them in software.
- The memory interface is very basic. It's suitable for cases where everything happens in a single cycle (e.g. an FPGA's on-chip RAM) but not much else.
- A small subset of machine mode is implemented. This is sufficient to
support timer driven interrupts.
The
threadsfirmware makes use of this.
Contains all of the Verilog for the RISC-V CPU. cpu.v holds the
top-level module. The ISA tests can be run from this directory with
./run_all_tests.sh. Icarus Verilog is
required to run the tests.
An example of a simple system built around the CPU. It consists of the
CPU plus RAM, UART and a timer. The system can be simulated by running
./sim.sh <firmware> from this
directory. Icarus Verilog is required
to run the simulation.
Contains firmware for the system. Building the firmware requires the GNU RISC-V compiler toolchain.
Holds a top-level module and Makefile that support synthesising the
system for the TinyFPGA BX
board. This
requires
Yosys,
nextpnr and
the IceStorm tools for
synthesis, and tinyprog for
programming the board. Use FW=<firmware> make prog to run synthesis
with a particular firmware and program the FPGA with the resulting
bitstream.
The riscv-tests assembled such that they can be run on this implementation.