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L3 update -- p9_sbe_instruct_start
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Change-Id: I2c501b01f8bf819f2610dcf55a9225bb70e19c18
RTC:139623
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42110
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42120
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@ibmthi @dcrowell77
ibmthi authored and dcrowell77 committed Jun 23, 2017
1 parent b504bd6 commit 04ee6e9
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Showing 2 changed files with 11 additions and 12 deletions.
13 changes: 6 additions & 7 deletions src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -24,14 +24,14 @@
/* IBM_PROLOG_END_TAG */
///
/// @file p9_sbe_instruct_start.C
/// @brief
/// Starts instructions on 1 core, thread 0.
/// Thread 0 will be started at CIA scan flush value of 0.
///
/// @brief Starts instructions on master core, thread 0.
/// Thread 0 will be started at CIA scan flush value of 0.
//
// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: HB
//

Expand All @@ -56,12 +56,11 @@ extern "C"
FAPI_INF("Starting instruction on thread 0");
FAPI_TRY(p9_thread_control(i_target, 0b1000, PTC_CMD_START, false,
l_rasStatusReg, l_state),
"p9_sbe_instruct_start: p9_thread_control() returns an error");
"p9_thread_control() returns an error");

fapi_try_exit:
FAPI_DBG("Exiting ...");
return fapi2::current_err;
}

} // extern "C"
/* End: */
10 changes: 5 additions & 5 deletions src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -23,13 +23,13 @@
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file p9_sbe_instruct_start.C
/// @brief Placeholder for overrides needed to step the core from cache-contained execution to expand to memory
/// @file p9_sbe_instruct_start.H
/// @brief Starts instructions on master core, thread 0.
///
// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: HB

#ifndef _PROC_SBE_INSTRUCT_START_H_
Expand All @@ -55,7 +55,7 @@ extern "C"
// Hardware Procedure
//------------------------------------------------------------------------------
///
/// @brief Calls thread_control to start instruction on thread 0.
/// @brief Calls thread_control to start instruction on master core, thread 0.
/// This is to be called during IPL (istep 5.2)
///
/// @param[in] i_target Reference to core target
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