PRD: Nimbus DD1.0 workaround for cache CEs

Change-Id: I5cab640c9525a710aad751a5a099c27986744cbb
CQ: SW380162
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36529
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36566
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

src/usr/diag/prdf/common/plat/p9/p9_ex.rule

@@ -723,7 +723,7 @@ group gL3FIR filter singlebit, cs_root_cause
     /** L3FIR[28]
      *  L3 LRU array parity error
      */
-    (rL3FIR, bit(28)) ? self_th_1;
+    (rL3FIR, bit(28)) ? l3_lru_parity_error;
 
     /** L3FIR[29]
      *  L3 cache congruence cache deleted

src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule

@@ -28,6 +28,7 @@ actionclass l3_cache_ce
     calloutSelfHigh;
     threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L3_CACHE_CES) );
     funccall("L3CE");
+    funccall("cacheCeWorkaround");
 };
 
 actionclass l3_cache_ue
@@ -39,13 +40,21 @@ actionclass l3_dir_ce
 {
     calloutSelfHigh;
     threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L3_DIR_CES) );
+    funccall("cacheCeWorkaround");
+};
+
+actionclass l3_lru_parity_error
+{
+    self_th_1;
+    funccall("cacheCeWorkaround");
 };
 
 actionclass l2_cache_ce
 {
     calloutSelfHigh;
     threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L2_CACHE_CES) );
-#    funccall("L2CE"); TODO: RTC 152593
+    funccall("L2CE");
+    funccall("cacheCeWorkaround");
 };
 
 actionclass l2_cache_ue

src/usr/diag/prdf/common/plat/p9/prdfP9Ex.C

@@ -168,6 +168,44 @@ int32_t PostAnalysis( ExtensibleChip * i_exChip,
 }
 PRDF_PLUGIN_DEFINE( p9_ex, PostAnalysis );
 
+/**
+ * @brief  For L2/L3 Cache CEs, L3 Directory CEs, and L3 LRU Parity Errors.
+ * @param  i_chip EX chip.
+ * @param  io_sc  Step code data struct.
+ * @return SUCCESS always
+ */
+int32_t cacheCeWorkaround( ExtensibleChip * i_chip,
+                           STEP_CODE_DATA_STRUCT & io_sc )
+{
+    // WORKAROUND: Nimbus DD1.x only.
+    if ( TARGETING::MODEL_NIMBUS == getChipModel(i_chip->getTrgt()) &&
+         0x20                    >  getChipLevel(i_chip->getTrgt()) )
+    {
+        // If we are unable to issue any more line deletes, mask the attention
+        // and do not make the error log predictive.
+        if ( io_sc.service_data->IsAtThreshold() )
+            io_sc.service_data->clearServiceCall();
+    }
+    // END WORKAROUND
+
+    return SUCCESS;
+
+} PRDF_PLUGIN_DEFINE( p9_ex, cacheCeWorkaround );
+
+/**
+ * @brief  L2FIR[0] - CE detected on L3 cache read
+ * @param  i_chip EX chip.
+ * @param  io_sc  Step code data struct.
+ * @return SUCCESS always
+ */
+int32_t L2CE( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc )
+{
+    // TODO: RTC 152593 add line delete support
+
+    return SUCCESS;
+
+} PRDF_PLUGIN_DEFINE( p9_ex, L2CE );
+
 /**
  * @brief Handle an L3 CE
  * @param i_chip Ex chip.