Istep4: add enable auto special wakeup after core is up

Change-Id: Ia4e85a2c8054ac2abcd1dca16bd73b28cb48f6c3
Original-Change-Id: I165c99b16998b1c4961008db4bcf054330209e8c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31566
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37042
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H

@@ -275,8 +275,9 @@ enum SLAVE_CONFIG_DEFS
 #define EX_1_CME_SCOM_SICR_CLEAR         EX_1_CME_SCOM_SICR_SCOM1
 #define EX_0_CME_SCOM_SICR_OR            EX_0_CME_SCOM_SICR_SCOM2
 #define EX_1_CME_SCOM_SICR_OR            EX_1_CME_SCOM_SICR_SCOM2
-#define CME_LCL_SICR_OR                  0xc0000510
-#define CME_LCL_SICR_CLR                 0xc0000518
-#define CME_LCL_SISR                     0xc0000520
+#define EX_0_CME_SCOM_LMCR_CLEAR         EX_0_CME_SCOM_LMCR_SCOM1
+#define EX_1_CME_SCOM_LMCR_CLEAR         EX_1_CME_SCOM_LMCR_SCOM1
+#define EX_0_CME_SCOM_LMCR_OR            EX_0_CME_SCOM_LMCR_SCOM2
+#define EX_1_CME_SCOM_LMCR_OR            EX_1_CME_SCOM_LMCR_SCOM2
 
 #endif  // __P9_HCD_COMMON_H__