WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modes

Change-Id: I6a6803cc0f3571d41ae3e5fa501b89609b88d525
CQ: HW401811
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36063
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36153
Tested-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -1970,6 +1970,23 @@
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW401811</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1: Silly Plutonium
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW400898</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -2020,7 +2037,7 @@
       </chip>
     </chipEcFeature>
   </attribute>
-
+  <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW363780</id>>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -2038,7 +2055,41 @@
       </chip>
     </chipEcFeature>
   </attribute>
-
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW403465</id>>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1: L1 access latency increases when data footprint should still
+                  be within L1 cache size. Revert L1 LRU changes
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW402145</id>>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1: Husky Dinosaur
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->
   <!-- ******************************************************************** -->