Hostboot Base TCE Support

This commit adds the base support for hostboot to enable/disable the
use of TCEs.  It allows for the creation and managment of a TCE table
and also initializes the P9 processors to use this table.

Change-Id: Idb40f9df5a90d8b7e87b2f5b745cbe7e66109df2
RTC:145071
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32562
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

src/include/usr/intr/interrupt.H

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -144,6 +144,34 @@ namespace INTR
         MSG_INTR_ENABLE_PSI_INTR,   //!< Enable PSIHB Interrupts
     };
 
+
+    //Derived from 15.8 PSIHB Software Interfaces of the p9_cn_psi_hb_regs.pdf
+    //  (splintered off from the P9 Pervasive Workbook)
+    // -- shared with other code (like utiltce)
+    struct PSIHB_SW_INTERFACES_t
+    {
+        uint64_t psihbbar; //Host Bridge Base Address Register    - 0x0
+        uint64_t fspbar;   //FSP Base Address Register            - 0x8
+        uint64_t fspmmr;   //FSP Memory Mask Register             - 0x10
+        uint64_t tceaddr;  //TAR - TCE Address Register           - 0x18
+        uint64_t psihbcr;  //PSI Host Bridge Ctrl/Status Register - 0x20
+        uint64_t psisemr;  //PSIHB Status / Error Mask Register   - 0x28
+        uint64_t reserved2; //Unused / Reserved
+        uint64_t phbdsr;   //PSIHB Debug Setting register         - 0x38
+        uint64_t phbscr;   //PSI Host Bridge Ctrl/Status Register - 0x40
+        uint64_t phbccr;   //PSI Host Bridge clear ctl/status reg - 0x48
+        uint64_t dmaupaddr; //DMA Upper Address Register          - 0x50
+        uint64_t icr;      //Interrupt Control Register           - 0x58
+        uint64_t esbciaddr; //ESB CI Base Address                 - 0x60
+        uint64_t esbnotifyaddr; //ESB Notification Address        - 0x68
+        uint64_t ivtofforig; //IVT Offset Origin Register         - 0x70
+        uint64_t lsiintlevel; //LSI Intr Level Register (lab use  - 0x78
+        uint64_t lsiintstatus; //LSI Interrupt Status register    - 0x80
+        uint64_t reserved3; //Unused / Reserved                   - 0x88
+        uint64_t phbsecure; //PSI Host Bridge Secure Control reg  - 0x90
+    };
+
+
     /**
      * Register a message queue for an interrupt type
      * @param[in] i_msgQ The message queue

src/include/usr/runtime/runtime_reasoncodes.H

@@ -40,21 +40,14 @@ namespace RUNTIME
         MOD_HDATSERVICE_GET_STANDALONE_SECTION  = 0x06, /**< hdatservice.C */
         MOD_HDATSERVICE_GETHOSTDATASECTION  = 0x07, /**< hdatservice.C */
         MOD_HDATSERVICE_VERIFY_HDAT_ADDRESS  = 0x08, /**< hdatservice.C */
-        MOD_TCE_CREATE                  = 0x09,   /**< tce.C */
-        MOD_TCE_INIT_HDW                = 0x0A,   /**< tce.C */
-        MOD_TCE_ALLOCATE                = 0x0B,   /**< tce.C */
-        MOD_TCE_DEALLOCATE              = 0x0C,   /**< tce.C */
-        MOD_TCE_INIT                    = 0x0D,   /**< tce.C */
-        MOD_TCE_MAP                     = 0x0E,   /**< tce.C */
-        MOD_HDATSERVICE_FINDSPIRA       = 0x0F, /** hdatservice.C */
-        MOD_HDATSERVICE_UPDATE_SECTION_ACTUAL = 0x10, /**< hdatservice.C */
-        MOD_HDATSERVICE_MAPREGION       = 0x11, /**< hdatservice.C */
+        MOD_HDATSERVICE_FINDSPIRA       = 0x09, /** hdatservice.C */
+        MOD_HDATSERVICE_UPDATE_SECTION_ACTUAL = 0x0A, /**< hdatservice.C */
+        MOD_HDATSERVICE_MAPREGION       = 0x0B, /**< hdatservice.C */
 
         // customize_attrs_for_payload.C
         MOD_CUST_COMP_NON_PHYP_RT_TARGET = 0x12,
         MOD_CUST_CONF_HBRT_HYP_IDS       = 0x13,
         MOD_POPULATE_RTDATABYNODE        = 0x14,  /**< populate_hbruntime.C */
-
         MOD_PM_RT_LOAD_PM_COMPLEX        = 0x15,  /**< rt_pm.C */
         MOD_PM_RT_HCODE_UPDATE           = 0x16,  /**< rt_pm.C */
     };

src/include/usr/util/util_reasoncodes.H

@@ -40,6 +40,14 @@ namespace Util
         UTIL_LIDMGR_RT          = 0x06,
         UTIL_LIDMGR_CLEANUP     = 0x07,       // UtilLidMgr::cleanup
         UTIL_RT_CMDS            = 0x08,       // rt_cmds.C
+        UTIL_TCE_INIT_HDW       = 0x09,       // UtilTceMgr::initTceInHdw
+        UTIL_TCE_ALLOCATE       = 0x0A,       // UtilTceMgr::allocateTces
+        UTIL_TCE_DEALLOCATE     = 0x0B,       // UtilTceMgr::deallocateTces
+        UTIL_TCE_CREATE_TABLE   = 0x0C,       // UtilTceMgr::createTceTable
+        UTIL_TCE_DISABLE_TCES   = 0x0D,       // Util::UTIL_TCE_DISABLE_TCES
+        UTIL_TCE_MAP_PSIHB      = 0x0E,       // UtilTceMgr::mapPsiHostBridge
+        UTIL_TCE_UNMAP_PSIHB    = 0x0F,       // UtilTceMgr::unmapPsiHostBridge
+
     };
 
     enum ReasonCode
@@ -55,6 +63,17 @@ namespace Util
         UTIL_LIDMGR_UNLOAD_RC_FAIL   = UTIL_COMP_ID | 0x09,
         UTIL_LIDMGR_NOT_FOUND        = UTIL_COMP_ID | 0x0A,
         UTIL_LIDMGR_MM_FAIL          = UTIL_COMP_ID | 0x0B,
+        UTIL_TCE_INVALID_SIZE        = UTIL_COMP_ID | 0x0C,
+        UTIL_TCE_ADDR_NOT_ALIGNED    = UTIL_COMP_ID | 0x0D,
+        UTIL_TCE_DEV_MAP_FAIL        = UTIL_COMP_ID | 0x0E,
+        UTIL_TCE_DEV_UNMAP_FAIL      = UTIL_COMP_ID | 0x0F,
+        UTIL_TCE_NOT_ENOUGH_FREE_ENTRIES = UTIL_COMP_ID | 0x10,
+        UTIL_TCE_ENTRY_NOT_CONTIGUOUS    = UTIL_COMP_ID | 0x11,
+        UTIL_TCE_PREVIOUSLY_ALLOCATED    = UTIL_COMP_ID | 0x12,
+        UTIL_TCE_INVALID_COUNT       = UTIL_COMP_ID | 0x13,
+        UTIL_TCE_ALLOC_BLOCK_FAIL    = UTIL_COMP_ID | 0x14,
+        UTIL_TCE_BLOCK_UNMAP_FAIL    = UTIL_COMP_ID | 0x15,
+
     };
 };
 

src/include/usr/util/utiltce.H

@@ -0,0 +1,111 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/usr/util/utiltce.H $                              */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2013,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __TCEIF_H
+#define __TCEIF_H
+
+#include <stdint.h>
+#include <builtins.h>
+#include <errl/errlentry.H>
+#include <devicefw/userif.H>
+
+#define UTILTCE_TRACE_NAME "UTILTCE"
+
+namespace TCE
+{
+
+/*******************************************/
+/* General TCE Enable/Disable Functions    */
+/*******************************************/
+
+/**
+ * @brief Responsible for allocating TCEs
+ *
+ * @param[in] i_startingAddress - Starting physical address that the allocated
+ *                                TCEs will map to.
+ *                                Needs to be Page-Aligned or will fail.
+ * @param[in] i_size - Size of the address space that TCEs map to.
+ *                     Size must be less than (512K * PAGESIZE) or will fail.
+ *                     Assert if not greater than zero.
+ *
+ * Note:  First time this is called will cause TCE Table to be created and
+ *        the Processors to be setup to point at the TCE Table
+ *
+ * @return errlHndl_t - Return Error Handle if failed
+ *
+ */
+errlHndl_t utilAllocateTces(uint64_t i_startingAddress,
+                            size_t i_size);
+
+/**
+ * @brief Responsible for deallocating TCEs
+ *
+ * @param[in] i_startingAddress  Starting physical address of the TCEs that
+ *                               are to be deallocated from the TCE Table.
+ *                               Needs to be page-aligned or will fail.
+ * @param[in] i_size - Size of address space that the TCEs that are to
+ *                     be deallocated map to.
+ *                     Size must be less than (512K * PAGESIZE) or will fail.
+ *                     Assert if not greater than zero.
+ *
+ * @return errlHndl_t - Return Error Handle if failed
+ *
+ */
+errlHndl_t utilDeallocateTces(uint64_t i_startingAddress,
+                              size_t i_size);
+
+
+/**
+ * @brief Responsible for disabling TCEs on the system, including
+ *        clearing the TCE Table and disabling Processor settings
+ *
+ * @return errlHndl_t - Return Error Handle if failed
+ *
+ */
+errlHndl_t utilDisableTces(void);
+
+
+/******************************************************/
+/* Specific TCE Setup/Close Functions for PAYLOAD     */
+/******************************************************/
+
+/**
+ * @brief Responsible for Setting up TCEs for PAYLOAD
+ *
+ * @return errlHndl_t - Return Error Handle if failed
+ *
+ */
+errlHndl_t utilSetupPayloadTces(void);
+
+/**
+ * @brief Responsible for closing the TCEs for PAYLOAD
+ *
+ * @return errlHndl_t - Return Error Handle if failed
+ *
+ */
+errlHndl_t utilClosePayloadTces(void);
+
+};
+
+#endif

src/include/usr/vmmconst.h

@@ -228,10 +228,11 @@ enum BlockPriority
 #define DUMP_TEST_MEMORY_ADDR (MPIPL_ATTR_DATA_ADDR + MPIPL_ATTR_DATA_SIZE)
 #define DUMP_TEST_MEMORY_SIZE  (4*MEGABYTE)
 
-/** Location of the TCE Table */
-#define TCE_TABLE_ADDR  (90*MEGABYTE)
+/** Physical memory location of the TCE Table */
+/** - needs to be aligned on 4MB boundary     */
+#define TCE_TABLE_ADDR  (88*MEGABYTE)
 
-// The size if 512K bytes of entries each uint64_t or 8 bytes in size.
+/** The TCE Table size is 512K entries each uint64_t (8 bytes) in size */
 #define TCE_TABLE_SIZE  ((512*KILOBYTE)*sizeof(uint64_t))
 
 #endif /* _VMMCONST_H */

src/usr/initservice/istepdispatcher/istepdispatcher.C

@@ -2099,17 +2099,19 @@ errlHndl_t  IStepDispatcher::handleCoalesceHostMsg()
 {
     TRACFCOMP(g_trac_initsvc, ENTER_MRK"IStepDispatcher::handleCoalesceHostMsg");
 
-    // Ensure the library is loaded
-    errlHndl_t err = VFS::module_load("libestablish_system_smp.so");
 
+    // Ensure the library is loaded
+    //@TODO RTC:164474
+    //errlHndl_t err = VFS::module_load("libestablish_system_smp.so");
+    errlHndl_t err = NULL;
     if (err)
     {
         TRACFCOMP(g_trac_initsvc, "handleCoalesceHostMsg: Error loading module, PLID = 0x%x",
                   err->plid());
     }
     else
     {
-        //@TODO RTC:133831
+        //@TODO RTC:164474
         //err = ESTABLISH_SYSTEM_SMP::call_host_coalesce_host();
         if (err)
         {

src/usr/intr/intrrp.H

@@ -264,29 +264,6 @@ namespace INTR
                 };
             };
 
-            //Derived from 15.8 PSIHB Software Interfaces of the
-            //  P9 Pervasive Workbook
-            struct PSIHB_SW_INTERFACES_t
-            {
-                uint64_t psihbbar; //Host Bridge Base Address Register    - 0x0
-                uint64_t fspbar;   //FSP Base Address Register            - 0x8
-                uint64_t fspmmr;   //FSP Memory Mask Register             - 0x10
-                uint64_t reserved1; //Unused / Reserved
-                uint64_t psihbcr;  //PSI Host Bridge Ctrl/Status Register - 0x20
-                uint64_t psisemr;  //PSIHB Status / Error Mask Register   - 0x28
-                uint64_t reserved2; //Unused / Reserved
-                uint64_t phbdsr;   //PSIHB Debug Setting register         - 0x38
-                uint64_t phbscr;   //PSI Host Bridge Ctrl/Status Register - 0x40
-                uint64_t phbccr;   //PSI Host Bridge clear ctl/status reg - 0x48
-                uint64_t dmaupaddr; //DMA Upper Address Register          - 0x50
-                uint64_t icr;      //Interrupt Control Register           - 0x58
-                uint64_t esbciaddr; //ESB CI Base Address                 - 0x60
-                uint64_t esbnotifyaddr; //ESB Notification Address        - 0x68
-                uint64_t ivtofforig; //IVT Offset Origin Register         - 0x70
-                uint64_t lsiintlevel; //LSI Int Level Register (lab use)  - 0x78
-                uint64_t lsiintstatus; //LSI Interrupt Status register    - 0x80
-            };
-
             //Found in the PC Register Specification Document
             struct XIVE_IC_THREAD_CONTEXT_t
             {

src/usr/isteps/istep16/call_host_ipl_complete.C

@@ -44,6 +44,7 @@
 #include    <targeting/attrrp.H>
 #include    <sys/internode.h>
 #include    <runtime/runtime.H>
+#include    <util/utiltce.H>
 
 using   namespace   ERRORLOG;
 using   namespace   TARGETING;
@@ -63,6 +64,20 @@ void* call_host_ipl_complete (void *io_pArgs)
                "call_host_ipl_complete entry" );
     do
     {
+        // Setup the TCEs needed for the FSP to DMA the PAYLOAD
+/*      @TODO RTC 168745 - make this call when FSP is ready for TCE Support
+ *                         and add check that we're on a FSP system
+ *      NOTE:  add check to do this only on FSP-based systems
+ *        l_err = TCE::utilSetupPayloadTces();
+ *
+ *       if( l_err )
+ *       {
+ *           TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ *                      ERR_MRK"TCE::utilSetupPayloadTces failed");
+ *           break;
+ *       }
+ */
+
         // Initialize the RUNTIME DATA attributes
         // that HDAT needs to allocate memory for us.
         // -----------------------------------------