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L3 update -- p9_suspend_io
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  - Update headers/comments
  - Added error traces to FAPI_TRY call
  - Review error FFDC and callout

Change-Id: I7b984cf8c6dd9fdd6a55a52a9f95bf6a8461d8c8
RTC:151595
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41301
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41303
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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@ibmthi @sgupta2m
ibmthi authored and sgupta2m committed Jun 26, 2017
1 parent 12e4bb3 commit 0df81aa
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170 changes: 78 additions & 92 deletions src/import/chips/p9/procedures/hwp/nest/p9_suspend_io.C
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Original file line number Diff line number Diff line change
Expand Up @@ -29,102 +29,72 @@
// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: HB

//-----------------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------------
#include <p9_suspend_io.H>
#include "p9_misc_scom_addresses.H"
#include "p9_misc_scom_addresses_fld.H"

//---------------------------//
// Function definitions //
//---------------------------//
//------------------------------------------------------------------------------
// name: p9_suspend_io
//------------------------------------------------------------------------------
// purpose:
// Freeze PEC and drive reset to PHB to suspend all IO traffic.
//
// parameters:
// 'i_target' is reference to chip target
// 'i_enable_suspend' is Boolean flag indicating whether you're running this procedure during MPIPL (true) or non-MPIPL (false)
//
// returns:
// FAPI_RC_SUCCESS (success, forced PCIe PHBs into reset)
// RC_P9_PBCQ_CQ_NOT_IDLE (error, timed out while waiting for traffic to become idle for PBCQ of PCIe controller)
// (Note: refer to file eclipz/chips/p9/working/procedures/xml/error_info/p9_suspend_io_errors.xml)
// getscom/putscom fapi errors
// fapi error assigned from eCMD function failure
//
//------------------------------------------------------------------------------
#include <p9_misc_scom_addresses.H>
#include <p9_misc_scom_addresses_fld.H>

///
/// @brief p9_suspend_io procedure entry point
/// See doxygen in p9_suspend_io.H
///
fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const bool i_enable_mpipl)
{
FAPI_DBG("Start MPIPL Procedure");

bool found_freeze_err; //true: found err that freezes PBCQ; otherwise false
uint32_t l_poll_counter; //Number of iterations while polling for inbound_active and outbound_active
uint32_t l_cur_fir_bit = 0; //Counter use to track freeze bits read.
bool found_freeze_err; // true: found err that freezes PBCQ; otherwise false
uint32_t l_poll_counter; // # of iterations while polling for inbound_active and outbound_active
uint32_t l_cur_fir_bit = 0; // Counter use to track freeze bits read.
uint64_t act0_bits;
uint64_t act1_bits;

fapi2::buffer<uint64_t> l_buf = 0;
fapi2::buffer<uint64_t> l_buf2 = 0;
auto l_phb_chiplets_vec = i_target.getChildren<fapi2::TARGET_TYPE_PHB>();
FAPI_DBG("PHB target vec size: %#x\n", l_phb_chiplets_vec.size());
uint8_t l_phb_id = 0;
uint8_t l_fabric_group_id = 0;

FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id))
auto l_phb_chiplets_vec = i_target.getChildren<fapi2::TARGET_TYPE_PHB>();
FAPI_DBG("PHB target vec size: %#x", l_phb_chiplets_vec.size());

fapi2::ATTR_CHIP_EC_FEATURE_HW363246_Type l_hw363246;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW363246,
i_target,
l_hw363246),
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW363246)");

//Loop through all PHBs configured
for (auto l_phb_chiplets : l_phb_chiplets_vec)
{
//Get the PHB id
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_phb_chiplets, l_phb_id));

//TODO SW384392 ZZ workaroud
//This HWP is ran on the SBE and the SBE does not know what PHBs are functional or not
//This causes this HWP to do scoms to targets that are not functional. This workaround
// needs to be removed when the SBE can reliably tell us what PHBs are functional
if(l_fabric_group_id == 0)
{
if(l_phb_id == 0x5)
{
continue;
}
}
else if(l_fabric_group_id == 1)
{
if(l_phb_id == 0x5 || l_phb_id == 0x4)
{
continue;
}
}
// Get the PHB id
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_phb_chiplets, l_phb_id),
"Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS");

//****************************************************************************************************************
//STEP #1: nop
// STEP #1: nop
//****************************************************************************************************************

//****************************************************************************************************************
//Recov_2: Force PEC into Freeze mode by writing into SW Freeze bit in PCI NEST FIR(26), if PEC not already frozen.
//****************************************************************************************************************
//******************************************************************************************************************
// Recov_2: Force PEC into Freeze mode by writing into SW Freeze bit in PCI NEST FIR(26), if PEC not already frozen.
//******************************************************************************************************************

//Initially, start with no error found that freezes PEC
found_freeze_err = false;

FAPI_DBG("PHB%i: Recov_2 - Force freeze the PEC if not already frozen.", l_phb_id);

//Read PCI Nest FIR Action0 register and put contents into l_buf
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIRACTION0_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIRACTION0_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_NFIRACTION0_REG);
FAPI_DBG("PHB%i: PCI Nest FIR Action0 Register %#lx", l_phb_id, l_buf());
act0_bits = l_buf;

//Read PCI Nest FIR Action1 register and put contents into l_buf
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIRACTION1_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIRACTION1_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_NFIRACTION1_REG);
FAPI_DBG("PHB%i: PCI Nest FIR Action1 Register %#lx", l_phb_id, l_buf());
act1_bits = l_buf;

Expand All @@ -133,15 +103,17 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
FAPI_DBG("PHB%i: PCI Nest FIR Freeze Bits %#lx", l_phb_id, l_buf2());

//Read PCI Nest FIR register and put contents into l_buf
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_NFIR_REG);
FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());

//Inspect which FIR bits are set AND if action is set to Freeze
while (l_cur_fir_bit < PHB_NFIR_REG_NFIRNFIR_LEN)
{
if(l_buf.getBit(l_cur_fir_bit) && l_buf2.getBit(l_cur_fir_bit))
{
FAPI_DBG("PHB%i: PEC is already frozen. PCI Nest FIR[%u] is asserted.", l_phb_id, l_cur_fir_bit);
FAPI_DBG("PHB%i: PEC is already frozen. PCI Nest FIR[%u] is asserted.",
l_phb_id, l_cur_fir_bit);
found_freeze_err = true;
break;
}
Expand All @@ -158,7 +130,8 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
l_buf = 0;
l_buf.setBit<PHB_NFIR_REG_SW_DEFINED_FREEZE>();
FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_NFIR_REG_OR, l_buf));
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_NFIR_REG_OR, l_buf),
"Error from putScom (0x%.16llX)", PHB_NFIR_REG_OR);
}

FAPI_DBG("PHB%i: Successfully put PEC into freeze state", l_phb_id);
Expand All @@ -172,24 +145,27 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
l_buf = 0;
l_buf.setBit<PHB_PHBRESET_REG_PE_ETU_RESET>();
FAPI_DBG("PHB%i: PHB Reset Register %#lx", l_phb_id, l_buf());
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_PHBRESET_REG, l_buf));

FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_PHBRESET_REG, l_buf),
"Error from putScom (0x%.16llX)", PHB_PHBRESET_REG);
FAPI_DBG("PHB%i: Successfully put PHB into reset", l_phb_id);

//****************************************************************************************************************
//Recov_4: Poll the CQ Status until all actively working DMA/CI operations are done by waiting for bits[0:1] = 00
//****************************************************************************************************************
FAPI_DBG("PHB%i: Recov_4 - Start polling for inbound_active and outbound_active state machines to become idle.",
l_phb_id);

l_poll_counter = 0; //Reset poll counter

while (l_poll_counter < MAX_NUM_POLLS)
{
l_poll_counter++;
FAPI_TRY(fapi2::delay(PBCQ_NANO_SEC_DELAY, PBCQ_SIM_CYC_DELAY), "fapiDelay error.");
FAPI_TRY(fapi2::delay(PBCQ_NANO_SEC_DELAY, PBCQ_SIM_CYC_DELAY),
"fapiDelay error.");

//Read PBCQ General Status Register and put contents into l_buf
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_CQSTAT_REG, l_buf), "Could not retrieve PHB_CQSTAT_REG.");
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_CQSTAT_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_CQSTAT_REG);
FAPI_DBG("PHB%i: PBCQ General Status Register %#lx", l_phb_id, l_buf());

//Check for bits 0 (inbound_active) and 1 (outbound_active) to become deasserted
Expand All @@ -205,10 +181,14 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
FAPI_DBG("PHB%i: inbound_active and outbound_active status (poll counter = %d).", l_phb_id, l_poll_counter);
fapi2::buffer<uint64_t> l_buf3 = 0;

FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf2));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf2),
"Error from getScom (0x%.16llX)", PHB_NFIR_REG);

FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf2());

FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_PHBRESET_REG, l_buf3));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_PHBRESET_REG, l_buf3),
"Error from getScom (0x%.16llX)", PHB_PHBRESET_REG);

FAPI_DBG("PHB%i: PHB Reset Register %#lx", l_phb_id, l_buf3());

FAPI_ASSERT(l_poll_counter < MAX_NUM_POLLS,
Expand All @@ -220,7 +200,7 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
.set_PHB_RESET_DATA(l_buf3)
.set_CQ_STAT_ADDR(PHB_CQSTAT_REG)
.set_CQ_STAT_DATA(l_buf),
"PHB%i: PBCQ CQ Status did not clear. It should!", l_phb_id);
"PHB%i: PBCQ CQ Status did not clear.", l_phb_id);


//****************************************************************************************************************
Expand All @@ -229,14 +209,15 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
FAPI_DBG("PHB%i: Recov_5 - Clearing Base Address Enabled register.", l_phb_id);

//Clear BARE register
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_BARE_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_BARE_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_BARE_REG);
l_buf.clearBit<PHB_BARE_REG_PE_MMIO_BAR0_EN>()
.clearBit<PHB_BARE_REG_PE_MMIO_BAR1_EN>()
.clearBit<PHB_BARE_REG_PE_PHB_BAR_EN>()
.clearBit<PHB_BARE_REG_PE_INT_BAR_EN>();
FAPI_DBG("PHB%i: Base Address Enable Register %#lx", l_phb_id, l_buf());
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_BARE_REG, l_buf));

FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_BARE_REG, l_buf),
"Error from putScom (0x%.16llX)", PHB_BARE_REG);
FAPI_DBG("PHB%i: Successfully cleared BARE", l_phb_id);

//****************************************************************************************************************
Expand All @@ -247,31 +228,30 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
//Clear FIR bits of PCI FIR register
l_buf = (uint64_t)0x0;
FAPI_DBG("PHB%i: PCI FIR Register Clear %#lx", l_phb_id, l_buf());
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_PFIR_REG_AND, l_buf));
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_PFIR_REG_AND, l_buf),
"Error from putScom (0x%.16llX)", PHB_PFIR_REG_AND);

//Confirm FIR bits have been cleared
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_PFIR_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_PFIR_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_PFIR_REG);
FAPI_DBG("PHB%i: PCI FIR Register %#lx", l_phb_id, l_buf());

FAPI_DBG("PHB%i: Successfully cleared PCI FIR.", l_phb_id);

//****************************************************************************************************************
//Recov_7: Clear CERR Report 0/1 bits
//****************************************************************************************************************
FAPI_DBG("PHB%i: Recov_7 - Clearing CERR Report 0/1 bits.", l_phb_id);

// TODO: HW363246 this step appears in the v1.0 doc but failed PCB address

//Clear CERR Report 0/1 bits
//l_buf = (uint64_t)0x0;
//FAPI_DBG("PHB%i: CERR Report0 Register Clear %#lx", l_phb_id, l_buf());
//FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_CERR_RPT0_REG, l_buf));

//l_buf = (uint64_t)0x0;
//FAPI_DBG("PHB%i: CERR Report1 Register Clear %#lx", l_phb_id, l_buf());
//FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_CERR_RPT1_REG, l_buf));

// TODO: HW363246 this step appears in the v1.0 doc but failed PCB address
if (!l_hw363246)
{
// Clear any spurious cerr_rpt0/1 bits by writing
// 0xFFFFFFFF_FFFFFFFF
l_buf.flush<1>();
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_CERR_RPT0_REG, l_buf),
"Error from putScom PHB_CERR_RPT0_REG");
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_CERR_RPT1_REG, l_buf),
"Error from putScom PHB_CERR_RPT1_REG");
}

FAPI_DBG("PHB%i: Succesfully cleared CERR Report 0/1 bits.", l_phb_id);

Expand All @@ -281,17 +261,23 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
FAPI_DBG("PHB%i: Recov_8 - Clearing PCI Nest FIR.", l_phb_id);

//Clear FIR bits of PCI Nest FIR register
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_NFIR_REG);
FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
l_buf.invert();
FAPI_DBG("PHB%i: PCI Nest FIR Register Clear %#lx", l_phb_id, l_buf());
FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_NFIR_REG_AND, l_buf));

FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_NFIR_REG_AND, l_buf),
"Error from putScom (0x%.16llX)", PHB_NFIR_REG_AND);

//Confirm FIR bits have been cleared
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_NFIR_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_NFIR_REG);
FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());

FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_PFIR_REG, l_buf2));
FAPI_TRY(fapi2::getScom(l_phb_chiplets, PHB_PFIR_REG, l_buf2),
"Error from getScom (0x%.16llX)", PHB_PFIR_REG);

FAPI_DBG("PHB%i: PCI FIR Register %#lx", l_phb_id, l_buf2());

if (l_buf.getBit<PHB_NFIR_REG_NFIRNFIR, PHB_NFIR_REG_NFIRNFIR_LEN>())
Expand All @@ -303,7 +289,7 @@ fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
.set_NFIR_DATA(l_buf)
.set_PFIR_ADDR(PHB_PFIR_REG)
.set_PFIR_DATA(l_buf2),
"PHB%i: PCI Nest FIR Register did not clear. It should!", l_phb_id);
"PHB%i: PCI Nest FIR Register did not clear.", l_phb_id);
}


Expand Down
49 changes: 21 additions & 28 deletions src/import/chips/p9/procedures/hwp/nest/p9_suspend_io.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,12 @@
/* IBM_PROLOG_END_TAG */
///
/// @file p9_suspend_io.H
/// @brief Procedure to suspend PCIe traffic. (FAPI2)
/// @brief Procedure to suspend PCIe traffic.
///
// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Level: 3
// *HWP Consumed by: HB

#ifndef _P9_SUSPEND_IO_H_
Expand All @@ -51,39 +51,32 @@ typedef fapi2::ReturnCode (*p9_suspend_io_FP_t) (const fapi2::Target<fapi2::TARG
// Constant definitions
//-----------------------------------------------------------------------------------

const uint8_t PHB_NFIR_REG_SW_DEFINED_FREEZE = 26; //PCI Nest FIR Register bit26 for SW Freeze enablement

const uint32_t MAX_NUM_POLLS = 100; //Maximum number of iterations (So, 20ms * 100 = 2s before timeout)
const uint64_t PBCQ_NANO_SEC_DELAY =
40000000; //(40000000 ns = 20 ms) to wait for PBCQ inbound and outbound to become inactive
const uint64_t PBCQ_SIM_CYC_DELAY =
400000; //400,000 simulation cycles to wait for PBCQ inbound and outbound to become inactive
// PCI Nest FIR Register bit26 for SW Freeze enablement
const uint8_t PHB_NFIR_REG_SW_DEFINED_FREEZE = 26;
//Maximum number of iterations (So, 20ms * 100 = 2s before timeout)
const uint32_t MAX_NUM_POLLS = 100;
//(40000000 ns = 20 ms) to wait for PBCQ inbound/outbound to become inactive
const uint64_t PBCQ_NANO_SEC_DELAY = 40000000;
//400,000 simulation cycles to wait for PBCQ inbound/outbound to become inactive
const uint64_t PBCQ_SIM_CYC_DELAY = 400000;


extern "C" {

//-----------------------------------------------------------------------------------
// Function prototype
//-----------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// name: p9_suspend_io
//------------------------------------------------------------------------------
// purpose:
// Freeze PEC and drive reset to PHB to suspend all IO traffic.
//
// parameters:
// 'i_target' is reference to chip target
// 'i_enable_mpipl' is Boolean flag indicating whether you're running this procedure during MPIPL (true) or non-MPIPL (false)
//
// returns:
// FAPI_RC_SUCCESS (success, forced PCIe PHBs into reset)
// RC_P9_PBCQ_CQ_NOT_IDLE (error, timed out while waiting for traffic to become idle for PBCQ of PCIe controller)
// (Note: refer to file eclipz/chips/p9/working/procedures/xml/error_info/p9_suspend_io_errors.xml)
// getscom/putscom fapi errors
// fapi error assigned from eCMD function failure
//
//------------------------------------------------------------------------------
fapi2::ReturnCode p9_suspend_io(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const bool i_enable_mpipl);
///
/// @brief Freeze PEC and drive reset to PHB to suspend all IO traffic
///
/// @param[in] i_target Reference to chip proc target
/// @param[in] i_enable_mpipl true = running during MPIPL; false = otherwise.
///
/// @return fapi2:ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode p9_suspend_io(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_enable_mpipl);

} //extern"C"

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