Update behavioral description of ATTR_SECURITY_MODE attribute

- Update behavioral description of ATTR_SECURITY_MODE attribute

Change-Id: I34eacb3e541d8cec505713ed2e55a55fd872cbe5
RTC: 170650
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39569
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Dev-Ready: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39573
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml

@@ -462,8 +462,14 @@
 <attribute>
   <id>ATTR_SECURITY_MODE</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
-  <description>If SBE image has ATTR_SECURITY_MODE == 0b1, then leave SAB bit as is
-  Else ATTR_SECURITY_MODE == 0b0, then clear the SAB bit</description>
+  <description>SBE context: If SBE image has ATTR_SECURITY_MODE == 0b1, leave
+    SAB bit as is.  Otherwise (ATTR_SECURITY_MODE == 0b0), query mailbox scratch
+    register 3 bit 6 and if set, clear the SAB bit. Non-SBE context: If
+    ATTR_SECURITY_MODE == 0b1, do not attempt to clear the SAB bit via the FSI
+    path.  Otherwise (ATTR_SECURITY_MODE == 0b0), attempt to clear the SAB bit
+    via the FSI path.  Customer level chips will silently ignore such a request,
+    whereas early lab versions may honor it for debug purposes.
+  </description>
   <valueType>uint8</valueType>
   <platInit/>
   <writeable/>