Releases: open-power/snap
v1.5.1
Major Changes
No major changes - Still Vivado2018.1 is supported for both CAPI1.0 and CAPI2.0
Changes relative to v1.5.0
- Documentation updates
- add waveforms for debugging (#833)
- New example: hdl example added (#838)
- New example: hls_decimal_mult (#826)
- Add mechanism to specify HLS compiler flags in action hw Makefile
- Adapt SNAP build process to HLS Xilinx IP call
- Update 8K5 PSL rev006 to rev007
- Adding 2 VU9P cards (FX609/S241)
- Add memcpy_throughputs tests (#784)
- Use a 34 bits address width for nvme_ddr
- Implement full CAPI2.0 DMA performance (#771)
- NVMe: attempt to circumvent Xilinx SystemVerilog deficiency + fixing synthesis problem
- Simplify use of snap_env.sh variables (#764)
- Get rid of Critical warnings in create_nvme_host.tcl
- Adapting SNAP build process to capi2-bsp
- Enable S121B card (SPIx4 and BPIx16)
Fixes
NVMe functional model
Major Changes
❗️Xilinx Vivado version 2018.1 support, 2017.4 will no longer be tested regularly. The current PSL DCPs on the IBM Portal work with 2018.1 as well.
NVMe functional emulation model added. Lets users simulate actions that use NVMe. The model works with ncsim, but it still has issues with xsim.
Changes relative to v1.4.2
- NVMe functional emulation model added
- Documentation updates
- Allow Xcelium, Modelsim, Questa as experimental simulators (#732)
- N250S+: New CAPI 2.0 board support process (#733)
- New board support process rcxvup (#746)
- Semptian NSA121B updates
- CAPI 2.0 experimental support: ReflexCES XpressVUP card
- New example Hls_latency_eval (#744)
Fixes
HW Config: Adding DENALI_USED and forcing SDRAM for NVMe
Cloud build timing improvements
Major Changes
❗️Vivado versions prior to 2017.4 are no longer supported.
❗️PSL DCPs on the IBM Portal are updated to versions built with Vivado 2017.4. Older versions are no longer supported. Please download the current PSL DCPs.
Changes relative to v1.4.0
-
Cloud build process and pblock improvements
- Updated pblocks
- Make the build flow more consistent by keeping the static region locked.
This flow is recommended by Xilinx UG909 "Partial Reconfiguration" (p.42 "Software Flow"). - Add output registers (outer REGSLICE) to AXI crossbar to relax timing and reduce placement density
-
More N250S+ (CAPI 2.0) updates.
- 64B alignment supported
- PCIe patch fixed
-
New capability register is used to determine the host memory byte alignments supported by a certain design.
Fixes
Typos, comparisons, assignment fails. DCP file cleanup corrected
#711 SNAP Action: Support for N250SP
#717 SNAP SW: Add DMA size and Align
#715 N250SP Simulation works with snap_example_set -b11, supposed to fail
Cloud build pblock improvements, CAPI 2.0
Major Changes
❗️Vivado versions prior to 2017.4 are no longer supported.
❗️PSL DCPs on the IBM Portal are updated to versions built with Vivado 2017.4. Older versions are no longer supported. Please download the current PSL DCPs.
Changes relative to v1.4.0
-
Cloud build process and pblock improvements
- Updated pblocks
- Make the build flow more consistent by keeping the static region locked.
This flow is recommended by Xilinx UG909 "Partial Reconfiguration" (p.42 "Software Flow").
-
More N250S+ (CAPI 2.0) updates.
- 64B alignment supported
- PCIe patch fixed
-
New capability register is used to determine the host memory byte alignments supported by a certain design.
Fixes
#711 SNAP Action: Support for N250SP
#717 SNAP SW: Add DMA size and Align
New cards, cloud build, example action cleanup
Major Changes
❗️Vivado versions prior to 2017.4 are no longer supported.
❗️PSL DCPs on the IBM Portal are updated to versions built with Vivado 2017.4. Older versions are no longer supported. Please download the current PSL DCPs.
- More N250S+ (CAPI 2.0) updates.
Fixes
Known Issues
💥 see issues: https://github.com/open-power/snap/issues?q=is%3Aissue+is%3Aopen+label%3Abug
Last version tested with Vivado 2016.4
Major Changes
❗️Last version to still support Vivado 2016.4. Please upgrade to Vivado 2017.4 soon. The cloud build flow uses 2017.4 only.
❗️Simulating NVMe with Vivado 2017.4 using Cadence irun requires a patch of the export_simulation.tcl. See Xilinx AR #70597. Image build is not affected.
-
PSL Checkpoints: Vivado 2017.4 versions added. ❗️Older versions will be deprecated soon.
Please use the latest PSL checkpoints for CAPI SNAP from the IBM Portal for OpenPOWER -
More N250S+ (CAPI 2.0) updates.
- Simulation can be used now, also with SDRAM
- Ready for FPGA image build now, but example actions are not fully functional yet.
-
Documentation updates
-
Automatically select the matching PSLSE version for P8 CAPI 1.0 or P9 CAPI 2.0
Fixes
- N250S NVMe in cloud build
- Don't do implicit
make cleanif the configuration wasn't changed by amake snap_configcall
Known Issues
💥 see issues: https://github.com/open-power/snap/issues?q=is%3Aissue+is%3Aopen+label%3Abug
Simulation in Cloud mode
Major Changes
❗️ Supports only Vivado 2017.4 for cloud build flow!
- Circumvents a Xilinx issue so that simulation is possible in cloud build flow (using partial reconfiguration flow)
- Several changes driven by the move to Vivado 2017.4
- Unrelated to cloud: Updated the factory image and flashing documentation, also add N250S+ there.
Known Issues
💥 NVMe support bug #615
Vivado 2016.4 can still be used for non-cloud build flows
Cloud beta
Major Changes
- Support Vivado 2017.4
- Fixes and circumventions for bugs and changes in Vivado
- Routing and timing improvements
- Add better recovery for unexpected crashes and abort with Ctrl-C
- LLCMD terminate handling
- MMIO "abort" register bit handling
- DMA quiesce
- Software abort or LLCMD terminate while action is attached
=> action reset w/ DRAM controller reset
- Configuration: better user error handling
- Updated PSL DCPs to fix Flash reload issues when resetting a card through sysfs or reboot.
Please fetch the latest PSL checkpoints for SNAP from https://www.ibm.com/systems/power/openpower - NVMe action bugfixes and performance improvements
- Not related to cloud: Add N250S+ simulation (CAPI 2.0 with PSLSE)
Fixes wrap-up
- MMIO
- dynamic linking
- time calculation
Old PSL checkpoint for N250S fallback
- Still supporting the initial PSL checkpoint for N250S