Merge pull request #467 from riscv-boom/sboom-release

SonicBOOM Release README

README.md

@@ -1,38 +1,32 @@
+![](docs/figures/evolution.png)
+
 The Berkeley Out-of-Order RISC-V Processor [![CircleCI](https://circleci.com/gh/riscv-boom/riscv-boom.svg?style=svg)](https://circleci.com/gh/riscv-boom/riscv-boom)
 ====================================================================================================================================================================
 
-The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the
-[Chisel](https://chisel.eecs.berkeley.edu/) hardware construction language. While BOOM is primarily ASIC optimized, it is also usable on FPGAs.
-We support the FireSim flow to run BOOM at 90+ MHz on FPGAs on Amazon EC2 F1. Created at the University of California,
-Berkeley in the [Berkeley Architecture Research](https://bar.eecs.berkeley.edu/) group, its focus is to create a high
-performance, synthesizable, and parameterizable core for architecture research.
+The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the [Chisel](https://chisel.eecs.berkeley.edu/) hardware construction language.
+Created at the University of California,
+Berkeley in the [Berkeley Architecture Research](https://bar.eecs.berkeley.edu/) group, its focus is to create a high performance, synthesizable, and parameterizable core for architecture research.
+The current version of the BOOM microarchitecture ([SonicBOOM, or BOOMv3](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf)) is performance competitive with commercial high-performance out-of-order cores, achieving 6.2 CoreMarks/MHz.
+
+![](docs/figures/uarch.png)
+
 
 Feature | BOOM
 --- | ---
 ISA | RISC-V (RV64GC)
 Synthesizable |√
 FPGA |√
 Parameterized |√
-Floating Point (IEEE 754-2008) |√
-Atomic Memory Op Support |√
+IEEE 754 Floating Point |√
+Atomics |√
 Caches |√
 Virtual Memory |√
 Boots Linux |√
-Boots Fedora |√
-Privileged Arch v1.11 |√
-External Debug |√
+Runs SPEC |√
+CoreMark/MHz |6.2
 
-## Documentation and Information
-
-Please check out the BOOM website @ https://boom-core.org for the most up-to-date information.
-It contains links to the mailing lists, documentation, design spec., publications and more!
-
-**Website:** (www.boom-core.org)
-
-**Mailing List** (https://groups.google.com/forum/#!forum/riscv-boom)
-
-## Important!
 
+## IMPORTANT: Using BOOM
 This repository is **NOT A SELF-RUNNING** repository. To instantiate a BOOM core, please use the
 [Chipyard](https://github.com/ucb-bar/chipyard) SoC generator.
 
@@ -41,10 +35,29 @@ file in the top level directory of this repository. This file is mainly used for
 Chipyard should follow the correct version of rocket-chip. For most users, you should be able to
 clone Chipyard separately and follow the default Chipyard instructions (without having to use the `.hash` file).
 
-## Disclaimer!
+While BOOM is primarily ASIC-optimized, it is also usable on FPGAs.
+Chipyard provides infrastructure and documentation for deploying BOOM on AWS F1 FPGAs through FireSim.
 
-The RISC-V Privileged ISA, Platform, and Debug specs are still in flux. BOOM will do its best to
-stay up-to-date with it!
+## Documentation and Information
+
+Please check out the BOOM website @ https://boom-core.org for the most up-to-date information.
+It contains links to the mailing lists, documentation, design spec., publications and more!
+
+If you use BOOMv3 in your published work, please cite BOOM as
+
+```
+@article{zhaosonicboom,
+  title={SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine},
+  author={Zhao, Jerry and Korpan, Ben and Gonzalez, Abraham and Asanovic, Krste},
+  booktitle={Fourth Workshop on Computer Architecture Research with RISC-V},
+}
+```
+
+**Website:** (www.boom-core.org)
+
+**Mailing List** (https://groups.google.com/forum/#!forum/riscv-boom)
+
+## Disclaimer!
 
 BOOM is a work-in-progress and remains in active development.