[chisel3] Add IO wrapper.

src/main/scala/2bc-table.scala

@@ -77,13 +77,13 @@ abstract class PTable(
    ) extends Module
 {
    val index_sz = log2Up(num_entries)
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val s1_r_idx = UInt(INPUT, width = index_sz)
       val s2_r_out = UInt(OUTPUT, width = fetch_width)
       val stall    = Bool(INPUT)
       val update   = Decoupled(new BrTableUpdate(fetch_width, index_sz)).flip
-   }
+   })
 
    val ridx = Wire(UInt())
    val last_idx = RegNext(ridx)
@@ -170,13 +170,13 @@ class HTable(
 {
    private val ptable_idx_sz = log2Up(num_p_entries)
    private val num_h_entries = if (share_hbit) num_p_entries/2 else num_p_entries
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       // Update the h-table.
       val update   = Valid(new UpdateEntry(fetch_width, ptable_idx_sz)).flip
       // Enqueue an update to the p-table.
       val pwq_enq  = Decoupled(new BrTableUpdate(fetch_width, ptable_idx_sz))
-   }
+   })
 
    val h_table = Module(new SeqMem1rwTransformable(num_h_entries, fetch_width))
    val hwq = Module(new Queue(new UpdateEntry(fetch_width, ptable_idx_sz), entries=4))
@@ -216,15 +216,15 @@ class TwobcCounterTable(
    private val index_sz = log2Up(num_entries)
    private val num_h_entries = if (share_hbit) num_entries/2 else num_entries
 
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       // send read addr on cycle 0, get data out on cycle 2.
       val s1_r_idx = UInt(INPUT, width = index_sz)
       val s2_r_out = UInt(OUTPUT, width = fetch_width)
       val stall    = Bool(INPUT)
 
       val update   = Valid(new UpdateEntry(fetch_width, index_sz)).flip
-   }
+   })
 
    println ("\t\tBuilding (" +
       (num_entries * fetch_width * 2/8/1024) + " kB) 2-bit counter table for (" +

src/main/scala/bpd_pipeline.scala

@@ -71,7 +71,7 @@ class BranchPredInfo(implicit p: Parameters) extends BoomBundle()(p)
 class BranchPredictionStage(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p)
    with HasBoomCoreParameters
 {
-   val io = new BoomBundle()(p)
+   val io = IO(new BoomBundle()(p)
    {
       // Fetch0
       val ext_btb_req   = Valid(new PCReq).flip
@@ -100,7 +100,7 @@ class BranchPredictionStage(fetch_width: Int)(implicit p: Parameters) extends Bo
       val redirect      = Bool(INPUT)
       val status_prv    = UInt(INPUT, width = rocket.PRV.SZ)
       val status_debug  = Bool(INPUT)
-   }
+   })
 
    //************************************************
    // construct all of the modules

src/main/scala/brpredictor.scala

@@ -172,7 +172,7 @@ object BrPredictor
 
 abstract class BrPredictor(fetch_width: Int, val history_length: Int)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new BoomBundle()(p)
+   val io = IO(new BoomBundle()(p)
    {
       // the PC to predict
       val req_pc = UInt(INPUT, width = vaddrBits)
@@ -197,7 +197,7 @@ abstract class BrPredictor(fetch_width: Int, val history_length: Int)(implicit p
       val flush = Bool(INPUT)
       // privilege-level (allow predictor to change behavior in different privilege modes).
       val status_prv = UInt(INPUT, width = rocket.PRV.SZ)
-   }
+   })
 
    // the (speculative) global history wire (used for accessing the branch predictor state).
    val ghistory = Wire(Bits(width = history_length))
@@ -688,7 +688,7 @@ class BrobEntry(fetch_width: Int)(implicit p: Parameters) extends BoomBundle()(p
 // a 1 snapshot/cycle throughput.
 class BranchReorderBuffer(fetch_width: Int, num_entries: Int)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new BoomBundle()(p)
+   val io = IO(new BoomBundle()(p)
    {
       // connection to BOOM's ROB/backend/etc.
       val backend = new BrobBackendIo(fetch_width)
@@ -700,7 +700,7 @@ class BranchReorderBuffer(fetch_width: Int, num_entries: Int)(implicit p: Parame
       // TODO enable bypassing of information. See if there's a "match", and then forward the outcome.
       //val pred_req = Valid(new // from fetch, requesting if a prediction matches an inflight entry.
       //val pred_resp = Valid(new // from fetch, return a prediction
-   }
+   })
 
    println ("\tBROB (w=" + fetch_width + ") Size (" + num_entries + ") entries of " +
       Wire(new BpdResp).asUInt.getWidth + " bits (" +

src/main/scala/btb-sa.scala

@@ -184,7 +184,7 @@ class PCReq(implicit p: Parameters) extends BTBsaBundle()(p)
 // Set-associative branch target buffer.
 class BTBsa(implicit p: Parameters) extends BoomModule()(p) with HasBTBsaParameters
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       // req.valid is false if stalling (aka, we won't read and use BTB results, on cycle S1).
       // req.bits.addr is available on cycle S0.
@@ -207,7 +207,7 @@ class BTBsa(implicit p: Parameters) extends BoomModule()(p) with HasBTBsaParamet
       // HACK: prevent BTB updating/predicting during program load.
       // Easier to diff against spike which doesn't run debug mode.
       val status_debug = Bool(INPUT)
-   }
+   })
 
    private val lsb_sz = log2Up(coreInstBytes)
    private def getTag (addr: UInt): UInt = addr(tag_sz+idx_sz+lsb_sz-1, idx_sz+lsb_sz)

src/main/scala/dcacheshim.scala

@@ -51,7 +51,7 @@ class LoadReqSlotIo(implicit p: Parameters) extends BoomBundle()(p)
 // as "valid", since it also got sent to the datacache.
 class LoadReqSlot(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new LoadReqSlotIo()
+   val io = IO(new LoadReqSlotIo())
 
    val valid      = Reg(init=Bool(false))
    val was_killed = Reg(init=Bool(false))
@@ -183,11 +183,11 @@ class DCacheShim(implicit p: Parameters) extends BoomModule()(p)
    val max_num_inflight = MAX_LD_COUNT
    isPow2(max_num_inflight)
 
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val core = (new DCMemPortIO()).flip
       val dmem = new rocket.HellaCacheIO
-   }
+   })
 
    // we are going to ignore store acks (for now at least), so filter them out and only listen to load acks
    // we know the store succeeded if it was not nacked

src/main/scala/decode.scala

@@ -351,7 +351,7 @@ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle()(p)
 // Takes in a single instruction, generates a MicroOp (or multiply micro-ops over x cycles)
 class DecodeUnit(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new DecodeUnitIo
+   val io = IO(new DecodeUnitIo)
 
    val uop = Wire(new MicroOp())
    uop := io.enq.uop
@@ -444,13 +444,13 @@ class DecodeUnit(implicit p: Parameters) extends BoomModule()(p)
 
 class BranchDecode extends Module
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val inst    = UInt(INPUT, 32)
       val is_br   = Bool(OUTPUT)
       val is_jal  = Bool(OUTPUT)
       val is_jalr = Bool(OUTPUT)
-   }
+   })
 
    val bpd_csignals =
       rocket.DecodeLogic(io.inst,
@@ -498,7 +498,7 @@ class FetchSerializerIO(implicit p: Parameters) extends BoomBundle()(p)
 // TODO instead of counter, clear mask bits as instructions are finished?
 class FetchSerializerNtoM(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new FetchSerializerIO
+   val io = IO(new FetchSerializerIO)
 
    val counter = Reg(init = UInt(0, log2Up(FETCH_WIDTH)))
    val inst_idx = Wire(UInt())
@@ -594,7 +594,7 @@ class DebugBranchMaskGenerationLogicIO(implicit p: Parameters) extends BoomBundl
 
 class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       // guess if the uop is a branch (we'll catch this later)
       val is_branch = Vec(pl_width, Bool()).asInput
@@ -615,7 +615,7 @@ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) exten
       val flush_pipeline = Bool(INPUT)
 
       val debug = new DebugBranchMaskGenerationLogicIO().asOutput
-   }
+   })
 
    val branch_mask = Reg(init = UInt(0, MAX_BR_COUNT))
 

src/main/scala/execute.scala

@@ -89,8 +89,8 @@ abstract class ExecutionUnit(val num_rf_read_ports: Int
                             , val has_fpiu      : Boolean       = false
                             )(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new ExecutionUnitIO(num_rf_read_ports, num_rf_write_ports
-                               , num_bypass_stages, data_width)
+   val io = IO(new ExecutionUnitIO(num_rf_read_ports, num_rf_write_ports
+                               , num_bypass_stages, data_width))
 
    io.resp.map(_.bits.fflags.valid := Bool(false))
 

src/main/scala/fdiv.scala

@@ -21,10 +21,10 @@ import tile.FPConstants._
 
 class UOPCodeFDivDecoder extends Module
 {
-  val io = new Bundle {
+  val io = IO(new Bundle {
     val uopc = Bits(INPUT, UOPC_SZ)
     val sigs = new tile.FPUCtrlSigs().asOutput
-  }
+  })
 
    val N = BitPat("b0")
    val Y = BitPat("b1")

src/main/scala/fetch.scala

@@ -47,7 +47,7 @@ class FetchBundle(implicit p: Parameters) extends BoomBundle()(p)
 class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p)
    with HasBoomCoreParameters
 {
-   val io = new BoomBundle()(p)
+   val io = IO(new BoomBundle()(p)
    {
       val imem              = new rocket.FrontendIO
       val f1_btb            = Valid(new BTBsaResp).flip
@@ -72,7 +72,7 @@ class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p
 
       val resp              = new DecoupledIO(new FetchBundle)
       val stalled           = Bool(OUTPUT) // CODE REVIEW
-   }
+   })
 
    val bchecker = Module (new BranchChecker(fetchWidth))
    val FetchBuffer = Module(new Queue(gen=new FetchBundle,
@@ -634,7 +634,7 @@ class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p
 // Incoming signals may be garbage (if f2_valid not true); consumer will have to handle that scenario.
 class BranchChecker(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val req           = Valid(new PCReq)
 
@@ -658,7 +658,7 @@ class BranchChecker(fetch_width: Int)(implicit p: Parameters) extends BoomModule
       val ras_update    = Valid(new RasUpdate)
 
       val req_cfi_idx   = UInt(OUTPUT, width = log2Up(fetchWidth)) // where is cfi we are predicting?
-   }
+   })
 
    // Did the BTB mispredict the cfi type?
    // Did the BTB mispredict the cfi target?

src/main/scala/fpu.scala

@@ -22,10 +22,10 @@ import util.uintToBitPat
 // to the Rocket FPU-speak
 class UOPCodeFPUDecoder extends Module
 {
-  val io = new Bundle {
+  val io = IO(new Bundle {
     val uopc = Bits(INPUT, UOPC_SZ)
     val sigs = new FPUCtrlSigs().asOutput
-  }
+  })
 
    // TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?")
    val N = Bool(false)
@@ -127,11 +127,11 @@ class FpuReq()(implicit p: Parameters) extends BoomBundle()(p)
 
 class FPU(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val req = new ValidIO(new FpuReq).flip
       val resp = new ValidIO(new ExeUnitResp(65))
-   }
+   })
 
    // all FP units are padded out to the same latency for easy scheduling of the write port
    val fpu_latency = dfmaLatency

src/main/scala/fudecode.scala

@@ -294,14 +294,14 @@ object FDivRRdDecode extends RRdDecodeConstants
 
 class RegisterReadDecode(supported_units: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new BoomBundle()(p)
+   val io = IO(new BoomBundle()(p)
    {
       val iss_valid = Bool(INPUT)
       val iss_uop   = new MicroOp().asInput
 
       val rrd_valid = Bool(OUTPUT)
       val rrd_uop   = new MicroOp().asOutput
-   }
+   })
 
    // Issued Instruction
    val rrd_valid = io.iss_valid

src/main/scala/functional_unit.scala

@@ -169,7 +169,7 @@ abstract class FunctionalUnit(is_pipelined: Boolean
                               (implicit p: Parameters) extends BoomModule()(p)
    with HasBoomCoreParameters
 {
-   val io = new FunctionalUnitIo(num_stages, num_bypass_stages, data_width)
+   val io = IO(new FunctionalUnitIo(num_stages, num_bypass_stages, data_width))
 }
 
 

src/main/scala/imul.scala

@@ -12,14 +12,14 @@ import rocket.ALU._
 
 class IMul(imul_stages: Int) extends Module
 {
-   val io = new Bundle {
+   val io = IO(new Bundle {
       val valid = Bool(INPUT)
       val fn  = UInt(INPUT, SZ_ALU_FN)
       val dw  = UInt(INPUT, SZ_DW)
       val in0 = UInt(INPUT,  64)
       val in1 = UInt(INPUT,  64)
       val out = UInt(OUTPUT, 64)
-   }
+   })
 
    def FN(dw: UInt, fn: UInt) = io.dw === dw && io.fn === fn
    val sxl64 = FN(DW_64, FN_MULH) | FN(DW_64, FN_MULHSU)

src/main/scala/issue.scala

@@ -55,7 +55,7 @@ abstract class IssueUnit(
    (implicit p: Parameters)
    extends BoomModule()(p)
 {
-   val io = new IssueUnitIO(issue_width, num_wakeup_ports)
+   val io = IO(new IssueUnitIO(issue_width, num_wakeup_ports))
 
    //-------------------------------------------------------------
    // Set up the dispatch uops

src/main/scala/issue_slot.scala

@@ -47,7 +47,7 @@ class IssueSlotIO(num_wakeup_ports: Int)(implicit p: Parameters) extends BoomBun
 
 class IssueSlot(num_slow_wakeup_ports: Int)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new IssueSlotIO(num_slow_wakeup_ports)
+   val io = IO(new IssueSlotIO(num_slow_wakeup_ports))
 
    // slot invalid?
    // slot is valid, holding 1 uop

src/main/scala/lsu.scala

@@ -140,7 +140,7 @@ class LoadStoreUnitIO(pl_width: Int)(implicit p: Parameters) extends BoomBundle(
 
 class LoadStoreUnit(pl_width: Int)(implicit p: Parameters, edge: uncore.tilelink2.TLEdgeOut) extends BoomModule()(p)
 {
-   val io = new LoadStoreUnitIO(pl_width)
+   val io = IO(new LoadStoreUnitIO(pl_width))
 
    val num_ld_entries = NUM_LSU_ENTRIES
    val num_st_entries = NUM_LSU_ENTRIES
@@ -1377,14 +1377,14 @@ object LoadDataGenerator
 
 class ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val addr_matches    = UInt(INPUT, num_entries) // bit vector of addresses that match between the load and the SAQ
       val youngest_st_idx = UInt(INPUT, MEM_ADDR_SZ) // needed to get "age"
 
       val forwarding_val  = Bool(OUTPUT)
       val forwarding_idx  = UInt(OUTPUT, MEM_ADDR_SZ)
-   }
+   })
 
    // generating mask that zeroes out anything younger than tail
    val age_mask = Wire(Vec(num_entries, Bool()))

src/main/scala/prefetcher.scala

@@ -49,11 +49,11 @@ class CacheIO(implicit p: Parameters) extends BoomBundle()(p)
 
 class Prefetcher(implicit p: Parameters) extends BoomModule()(p)
 {
-   val io = new Bundle
+   val io = IO(new Bundle
    {
       val core_requests = (new ValidIO(new CoreRequest)).flip
       val cache = new CacheIO
-   }
+   })
 
 
    // ********** ENTER YOUR CODE HERE ************