[rc] Fixes for July RC

build.sbt

@@ -4,6 +4,8 @@ version := "1.0"
 
 name := "boom"
 
-scalaVersion := "2.11.6"
+scalaVersion := "2.12.4"
+
+scalacOptions ++= Seq("-Xsource:2.11")
 
 addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)

src/main/scala/exu/core.scala

@@ -142,7 +142,6 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    // Shim to DCache
    io.dmem <> dc_shim.io.dmem
    dc_shim.io.core <> exe_units.memory_unit.io.dmem
-   dc_shim.io.core.invalidate_lr := rob.io.com_xcpt.valid
 
    // Load/Store Unit & ExeUnits
    exe_units.memory_unit.io.lsu_io := lsu.io

src/main/scala/lsu/dcacheshim.scala

@@ -152,7 +152,7 @@ class DCMemPortIO(implicit p: Parameters) extends BoomBundle()(p)
    val brinfo  = new BrResolutionInfo().asOutput
    val nack    = new NackInfo().asInput
    val flush_pipe  = Bool(OUTPUT)   // exception or other misspec which flushes entire pipeline
-   val invalidate_lr = Bool(OUTPUT) // should the dcache clear ld/sc reservations?
+
    val load_miss = Bool(INPUT)      // Did a load suffer a cache miss? (not necessarily nacked, but no data).
    val ordered = Bool(INPUT)        // is the dcache ordered? (fence is done)
 
@@ -289,7 +289,7 @@ class DCacheShim(implicit p: Parameters) extends BoomModule()(p)
    io.dmem.s2_kill        := false.B
    io.dmem.s1_kill        := io.core.req.bits.kill || iflb_kill // kills request sent out last cycle
    io.dmem.req.bits.phys  := Bool(true) // we always use physical addresses (TLB is in LSU).
-   io.dmem.invalidate_lr  := io.core.invalidate_lr
+
 
    //------------------------------------------------------------
    // handle responses and nacks

src/main/scala/system/BoomSubsystem.scala

@@ -19,7 +19,7 @@ import freechips.rocketchip.amba.axi4._
 case object BoomTilesKey extends Field[Seq[boom.common.BoomTileParams]](Nil)
 
 trait HasBoomTiles extends HasTiles
-    with HasPeripheryPLIC
+    with CanHavePeripheryPLIC
     with CanHavePeripheryCLINT
     with HasPeripheryDebug { this: BaseSubsystem =>
   val module: HasBoomTilesModuleImp
@@ -37,7 +37,7 @@ trait HasBoomTiles extends HasTiles
 
     connectMasterPortsToSBus(boomCore, crossing)
     connectSlavePortsToCBus(boomCore, crossing)
-    connectInterrupts(boomCore, Some(debug), clintOpt, Some(plic))
+    connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt)
 
     boomCore
   }