Skip to content

Issues: riscv/sail-riscv

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

101 Open 95 Closed
101 Open 95 Closed
Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

VM code reads 8 bytes even for 4-byte PTEs
#459 opened Apr 26, 2024 by Timmmm
1
2
VM code doesn't check reserved bits of PTEs are zero
#457 opened Apr 24, 2024 by Timmmm
5
OpenOCD/GDB Support
#453 opened Apr 17, 2024 by TimMThomas
5
Implicit CSR writes are not logged
#450 opened Apr 15, 2024 by allenjbaum
Implementing callbacks in sail-riscv for state-changing events
#449 opened Apr 12, 2024 by kseniadobrovolskaia
Use newtype for physical and virtual addresses
#434 opened Mar 18, 2024 by Timmmm
Use result type instead of MemoryOpResult, TR_Result, and PTW_Result
#433 opened Mar 15, 2024 by Timmmm
9
Refactor duplicated floating point code for 16/32/64 bit floats
#432 opened Mar 13, 2024 by Timmmm
1
Remove redundant match expressions for word width
#429 opened Mar 11, 2024 by Timmmm
Switch forall to ranges/sets
#426 opened Mar 5, 2024 by Timmmm
1
Support for SystemVerilog compilation using sail -sv
#424 opened Mar 4, 2024 by torjeikenes
6
Sail model uses old asm mnmonics for vmandn and vmorn
#421 opened Mar 1, 2024 by mdhayter
Store Conditional can retire successfully even if atomics are disabled:
#419 opened Feb 29, 2024 by Timmmm
Remove etc directory
#418 opened Feb 29, 2024 by Timmmm
Remove instbits
#412 opened Feb 23, 2024 by Timmmm
4
CSRs should use scattered functions
#410 opened Feb 19, 2024 by Timmmm
2
Add comment explaining why the model doesn't use vectors for registers
#409 opened Feb 19, 2024 by Timmmm
2
Incremental OCaml builds don't work
#407 opened Feb 12, 2024 by Timmmm
1
is_CSR_defined has redundant privilege mode checks
#402 opened Feb 6, 2024 by Timmmm
1
Optimization
#401 opened Feb 5, 2024 by M20M19
3
Make file error
#399 opened Feb 2, 2024 by Ludini1
10
Another vector test suite, maybe add this to CI?
#391 opened Jan 18, 2024 by cfbolz
Logging state changes
#390 opened Jan 16, 2024 by allenjbaum
1
More rigorous handling of reset
#383 opened Jan 4, 2024 by Timmmm
4
Note on software structure
#382 opened Jan 3, 2024 by martinberger
7
ProTip! no:milestone will show everything without a milestone.