GitHub - sid137/eit-sequence: EIT Sequence for Labview FPGA

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 118 Commits
B Field control Signal		B Field control Signal
FPGA Bitfiles		FPGA Bitfiles
Phase Aquisition		Phase Aquisition
Pulse Acquisition		Pulse Acquisition
Raman Measure		Raman Measure
Tomography		Tomography
builds/exe		builds/exe
8-Point Average Parallel.vi		8-Point Average Parallel.vi
Acquisition_chopper.vi		Acquisition_chopper.vi
Add Timestamp to File and Directory.vi		Add Timestamp to File and Directory.vi
Convert Ticks to Time.vi		Convert Ticks to Time.vi
Create Data Path.vi		Create Data Path.vi
Divide by Two.vi		Divide by Two.vi
EIT Sequence.aliases		EIT Sequence.aliases
FPGA-no_chopper.vi		FPGA-no_chopper.vi
FPGAsubPulse - Copy.vi		FPGAsubPulse - Copy.vi
FPGAsubPulse.vi		FPGAsubPulse.vi
FPGAvi.vi		FPGAvi.vi
Front Panel.jpg		Front Panel.jpg
GraphTest.vi		GraphTest.vi
HostConvertTimetoTicks.vi		HostConvertTimetoTicks.vi
HostNoChopper.vi		HostNoChopper.vi
HostoldMain.vi		HostoldMain.vi
Loop Counter Timer.vi		Loop Counter Timer.vi
MOT EIT.aliases		MOT EIT.aliases
MOT2.aliases		MOT2.aliases
MOT2.lvlps		MOT2.lvlps
MOT2.lvproj		MOT2.lvproj
Memory Trigger Source.ctl		Memory Trigger Source.ctl
New Text Document.txt		New Text Document.txt
Notes.txt		Notes.txt
Phase Acq.ctl		Phase Acq.ctl
Plot Time Scale.vi		Plot Time Scale.vi
Scale Frequency from Freq.vi		Scale Frequency from Freq.vi
Scale Frequency.vi		Scale Frequency.vi
Sequence.ctl		Sequence.ctl
Signal Options.ctl		Signal Options.ctl
Simple Counter with Reset.vi		Simple Counter with Reset.vi
States.ctl		States.ctl
Stay when Set.vi		Stay when Set.vi
Test.aliases		Test.aliases
Toggle_Bit.png		Toggle_Bit.png
compilation.txt		compilation.txt
raman.txt		raman.txt
test.vi		test.vi