riscv: dts: starfive: add watchdog node

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
starfive-tech · Feb 15, 2022 · ef571fc · ef571fc
1 parent ca3cac1
commit ef571fc
Showing 1 changed file with 14 additions and 0 deletions.
diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi
@@ -136,6 +136,20 @@
 			reg-names = "control";
 		};
 
+		wdog: wdog@12480000 {
+			compatible = "starfive,si5-wdt";
+			reg = <0x0 0x12480000 0x0 0x10000>;
+			interrupt-parent = <&plic>;
+			interrupts = <80>;
+			interrupt-names = "wdog";
+			clocks = <&clkgen JH7100_CLK_WDT_CORE>,
+				<&clkgen JH7100_CLK_WDTIMER_APB>;
+			clock-names = "core_clk", "apb_clk";
+			clock-frequency = <50000000>;
+			timeout-sec = <15>;
+			status = "okay";
+		};
+
 		plic: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
 			compatible = "riscv,plic0";