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27 public repositories
matching this topic...
Updated
Oct 16, 2017
Verilog
A DDR3 to DDR3L (and vice-versa) converter
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Updated
May 10, 2020
Verilog
DDR3 controller for nMigen (WIP)
Updated
Dec 25, 2023
Python
A simple command line tool for reading and writing AT24/EE1004 SPD EEPROMs.
Updated
Sep 24, 2020
Python
4-Layer XC7Z010 DDR3 Layout
Lusin's Random-Access-Humor resulted in the creation of the RAM Overclocker!
Test SBC with Allwinner A13
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Updated
Dec 1, 2022
Verilog
SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
在FPGA中将图像数据输入到DDR3中,再输送到HDMI接口上进行显示。
将图像数据从以太网传输到DDR3,再传输到HDMI进行显示的vivado例程
Updated
May 8, 2023
OpenSCAD
Updated
Jul 19, 2023
OpenSCAD
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