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verilog

Here are 3,751 public repositories matching this topic...

logisim-evolution

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Apr 25, 2024
Java

chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Apr 26, 2024
Scala

openwifi

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Updated Apr 4, 2024
C

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power

Updated Mar 24, 2021
Verilog

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Apr 4, 2024
Assembly

verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Apr 27, 2024
C++

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Apr 26, 2024
C

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu fpga core processor riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Apr 18, 2024
Verilog

icestudio

FPGAwars / icestudio

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

Updated Apr 25, 2024
JavaScript

cocotb / cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

python test vhdl verification verilog uvm

Updated Apr 27, 2024
Python

SpinalHDL / SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

Updated Apr 27, 2024
Scala

pConst / basic_verilog

Must-have verilog systemverilog modules

Updated Mar 12, 2024
Verilog

neorv32

stnolting / neorv32

🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Updated Apr 27, 2024
C

analogdevicesinc / hdl

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Apr 26, 2024
Verilog

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Apr 25, 2024
Haskell

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Apr 27, 2024
Verilog

serv

olofk / serv

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Apr 9, 2024
Verilog

ZipCPU / zipcpu

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Mar 22, 2024
Verilog

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Apr 24, 2024
Python

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