Test suite designed to check compliance with the SystemVerilog standard.
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Updated
May 20, 2024 - SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
FPGA tool performance profiling
Sphinx Extension which generates various types of diagrams from Verilog code.
Python library for working Standard Delay Format (SDF) Timing Annotation files.
Repository containing common Makefiles for setting up conda environments.
An abstraction library for interfacing EDA tools
FPGA Assembly (FASM) Parser and Generator
Tool for graphically viewing FPGA bitstream files and their connection to FASM features.
Random ideas and interesting ideas for things we hope to eventually do.
Conda build recipes for the toolchains needed by LiteX / MiSoC firmware
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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