arch: arm: cortex_a_r: Improve support for big endian #72693
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zephyrbot
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carlocaione,
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ithinuel,
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@ithinuel please take a look |
carlocaione
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Comment on lines
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| #if defined(CONFIG_BIG_ENDIAN) | ||
| #define E_BIT (1 << 9) | ||
| #else | ||
| #define E_BIT (0 << 9) | ||
| #endif | ||
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|
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Set or un-set E_BIT in thread.c. This file is encoding the BIT position, so the E_BIT position is always 1 << 9 but only set for CONFIG_BIG_ENDIAN.
ithinuel
requested changes
Jun 12, 2024
arch/arm/core/cortex_a_r/thread.c
Outdated
| @@ -94,7 +94,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, | |||
| iframe->a3 = (uint32_t)p2; | |||
| iframe->a4 = (uint32_t)p3; | |||
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| iframe->xpsr = A_BIT | MODE_SYS; | |||
| iframe->xpsr = E_BIT | A_BIT | MODE_SYS; | |||
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Suggested change
| iframe->xpsr = E_BIT | A_BIT | MODE_SYS; | |
| #if defined(CONFIG_BIG_ENDIAN) | |
| iframe->xpsr = E_BIT | A_BIT | MODE_SYS; | |
| #else | |
| iframe->xpsr = A_BIT | MODE_SYS; | |
| #endif |
Comment on lines
29
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| #if defined(CONFIG_BIG_ENDIAN) | ||
| #define E_BIT (1 << 9) | ||
| #else | ||
| #define E_BIT (0 << 9) | ||
| #endif | ||
|
|
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Suggested change
| #if defined(CONFIG_BIG_ENDIAN) | |
| #define E_BIT (1 << 9) | |
| #else | |
| #define E_BIT (0 << 9) | |
| #endif | |
| #define E_BIT (1 << 9) |
|
These suggestions are essentially what @carlocaione is requesting. |
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ithinuel
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Jun 28, 2024
When this bit is not set, it defaults to 0 (little endian). This causes issues for big-endian devices, as data will be accessed using little endian. Signed-off-by: Sigmund Klåpbakken <sigmundklaa@outlook.com>
Sets the property `PROPERTY_OUTPUT_FORMAT` to `elf32-bigarm` when `CONFIG_BIG_ENDIAN` is set to `y`. Signed-off-by: Sigmund Klåpbakken <sigmundklaa@outlook.com>
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Fixed |
ithinuel
approved these changes
Jun 29, 2024
carlocaione
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Jul 4, 2024
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This enables support for big endian Cortex A/R devices. The pull request consists of two changes:
PROPERTY_OUTPUT_FORMATtoelf32-bigarmwhenCONFIG_BIG_ENDIAN=yCPSRregister, ensuring that the CPU stays in big endian mode when switching to the main thread. Without this, data accesses used the wrong endianness, causing a (very big) headache.The
CPSRissue was the only problem I noticed when porting theTMS570LS1224big endian Cortex R4F SoC. With this fixed, it seems to work completely fine. My setup is available at https://github.com/OrbitNTNU/zephyr-hw if that is relevant.