VHDL Code for FPGAs (With Some Verilog For Comparison)

This is a collection of code from CDA 4240C: Design of Digital Systems.

There is a separate Verilog folder since we studied the differences between it and VHDL at the end of the course.
My Projects were simulated and synthesized using Xilinx Vivado 2022.2
This code runs on the Nexys A7-100T FPGA Evaluation Board:

Name		Name	Last commit message	Last commit date
Latest commit History 189 Commits
Assets		Assets
VHDL		VHDL
Verilog		Verilog
.gitattributes		.gitattributes
README.md		README.md

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