This repo contains small size projects using NEXYS_A7 and Verilog
-
Notifications
You must be signed in to change notification settings - Fork 0
Choijh03/FPGA_NEXYS_A7_PROJECTS
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
No description or website provided.
Topics
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published