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Implemented a multi-cycle CPU with 54 MIPS instructions and CP0 coprocessor using Verilog language at the behavioral level. The design supports interrupts.

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MutiCycle-CPU

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Implemented a multi-cycle CPU with 54 MIPS instructions and CP0 coprocessor using Verilog language at the behavioral level. The design supports interrupts.

cpu multi-cycle cp0

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