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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity tb is | ||
end tb; | ||
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architecture sim of tb is | ||
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type SlvArray_t is array(integer range<>) of std_logic_vector; | ||
type UnsignedArray_t is array(integer range<>) of unsigned; | ||
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constant a : UnsignedArray_t(0 to 0)(0 downto 0) := (others => (others => '0')); | ||
constant b : SlvArray_t := SlvArray_t(a); | ||
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begin | ||
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process | ||
begin | ||
std.env.stop; | ||
end process; | ||
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end sim; |
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entity tb2 is | ||
end tb2; | ||
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architecture sim of tb2 is | ||
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type SlvArray_t is array(integer range<>) of bit_vector; | ||
type UnsignedArray_t is array(integer range<>) of bit_vector; | ||
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constant a : UnsignedArray_t(0 to 0)(0 downto 0) := (others => (others => '0')); | ||
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procedure p is | ||
constant b : SlvArray_t := SlvArray_t(a); | ||
begin | ||
report "p"; | ||
end p; | ||
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begin | ||
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process | ||
begin | ||
p; | ||
wait; | ||
end process; | ||
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end sim; |
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#! /bin/sh | ||
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. ../../testenv.sh | ||
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export GHDL_STD_FLAGS=--std=08 | ||
analyze tb.vhdl | ||
elab_simulate tb | ||
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analyze tb2.vhdl | ||
elab_simulate tb2 | ||
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clean | ||
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echo "Test successful" |