Enable RVV GEMM/IGEMM 7 x m4 in operator config

[bhbruce]

This PR aims to enable RVV GEMM/IGEMM/X32-PACKW in GEMM config.
It leads to enabling RVV implementation in operator API.

[bhbruce]

@alankelly @fbarchard Could you help to review it?
Also, I would like to ask about what's the appropriate way to enable RVV-only nr2 selection logic in following files.

src/operators/convolution-nhwc.c
1653:  const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config();
src/operators/dynamic-fully-connected-nc.c
215:  const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config();
src/operators/fully-connected-nc.c
754:  const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config();
src/operators/deconvolution-nhwc.c
898:  const struct xnn_gemm_config* gemm_nr2_config = xnn_init_f32_gemm_nr2_config();

The current logic determines to use nr2_config(half nr) if gemm_config->nr > output_channels.
For the RISC-V vector, I would like to specialize in either

gemm_nr2_config->nr <= output_channels
or
gemm_config->nr / 2 <= output_channels

However, there is no arch-specifc definition macro used in src/operators/.

[fbarchard]

nr 2 is an MRx2 GEMM - 2 floats wide.
On SSE and NEON that normally use 4 floats per vector it allows a faster GEMM.
But it is optional... any gemm can output NC of less than a full vector, and on RVV is shouldnt make a difference.

[bhbruce]

Hi @fbarchard @alankelly
Could you help to merge this PR?