There are breaking changes in this release from v1.1! They are called out with a
In order of recency:
- Screen position is now at the origin cx, cy == 0,0
⚠️ screen_start_x and screen_start_y no longer exist because they are 0- screen/frame width and height are still provided for knowing whether video is active
- Reset synchronous to clk_pixel is now supported
- The fast clock is now always DDR (5x as fast instead of 10x as fast)
⚠️ DDRIO parameter no longer exists⚠️ clk_pixel_x10 renamed to clk_pixel_x5- SDR users will need to double the divider in their PLL setups to halve the fast clock speed
- New video formats
- 4k30fps (95, 105)
- 1080p30fps (34)
- Rewritten TMDS serialization
⚠️ tmds_p and tmds_n is now just tmds⚠️ tmds_clk_p and tmds_clk_n is now just tmds_clk- Intel: use altlvds instead of handwritten serializer with altera_gpio_lite
- Xilinx: use OSERDESE2 instead of handwritten serializer
⚠️ Xilinx users! Ownership of OBUFDS has been moved outside of the hdmi module to the user side! See https://github.com/hdl-util/hdmi-demo/blob/master/top/sea/sea_top.sv#L50 for an example.- Why? Intel's altlvds automatically generates the tmds negative component and routes it to the correct pin, so unfortunately it can't be included in the hdmi module interface
- OSERDESE2 requires an initial reset and I've added one. If you want to reset it when the PLL/MMCM is ready you can do so via synchronous reset.
- other platforms: support (in theory) via ip-less tmds serializer
- Unrelated changes
- Migrate repo from Travis CI to GitHub Actions
- Minor fixes in testbenches